LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 34
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2-6E-7T144C
Manufacturer Part Number
LFE2-6E-7T144C
Description
FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
Manufacturer
Lattice
Datasheet
1.LFE2-70E-7F900C.pdf
(104 pages)
Specifications of LFE2-6E-7T144C
Number Of I/os
90
Maximum Operating Frequency
420 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TQFP-144
Minimum Operating Temperature
0 C
Factory Pack Quantity
300
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-6E-7T144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 34 of 104
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Lattice Semiconductor
Figure 2-28. Output and Tristate Block for Left, Right and Bottom Edges
DQSXFER
DQSXFER
ONEG1
ONEG0
ONEG1
ONEG0
OPOS1
OPOS0
OPOS1
OPOS0
(CLKA)
(CLKB)
ECLK1
ECLK2
ECLK1
ECLK2
CLKA
CLKB
CLK1
CLK1
TD
TD
* Shared with output register
Clock Transfer
Clock Transfer
Registers
Registers
D
D
D-Type*
D-Type*
D-Type
D-Type
D
D
Tristate Logic
Tristate Logic
Q
Q
Q
Q
*
*
D
D
Latch
Latch
Q
Q
0
1
0
1
0
1
0
1
2-31
Note: Simplified version does not show CE and SET/RESET details
0
1
0
1
0
1
0
1
D
D
D
D
D
D
D
D
/LATCH
/LATCH
/LATCH
/LATCH
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
Q
Q
Q
Q
Q
Q
Q
Q
LatticeECP2 Family Data Sheet
Comp PIO in LVDS I/O Pair
True PIO in LVDS I/O Pair
D
D
D
D
DDR Output
DDR Output
Latch
Latch
Latch
Latch
Registers
Registers
Q
Q
Q
Q
Output Logic
Output Logic
0
1
0
1
0
1
0
1
0
1
0
1
Programmable
Programmable
Control
Control
0
1
0
1
Architecture
0
1
0
1
DO
DO
TO
TO
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