LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 19

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
If none of the signals are selected for both clock and control then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Figure 2-15. Slice0 through Slice2 Clock Selection
Figure 2-16. Slice0 through Slice2 Control Selection
Edge Clock Routing
LatticeECP2 devices have a number of high-speed edge clocks that are intended for use with the PIOs in the
implementation of high-speed interfaces. There are eight edge clocks per device: two edge clocks per edge. Differ-
ent PLL and DLL outputs are routed to the two muxes on the left and right sides of the device. In addition, the
CLKINDEL signal (generated from the DLL_DEL block) is routed to all the edge clock muxes on the left and right
sides of the device. Figure 2-17 shows the selection muxes for these clocks.
Secondary Clock
Secondary Clock
Primary Clock
Routing
Routing
Vcc
Vcc
12
12
8
4
1
3
1
2-16
25:1
16:1
Clock to Slice
Slice Control
LatticeECP2 Family Data Sheet
Architecture