LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 30

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
Table 2-11. DSP Performance
For further information on the sysDSP block, please see details of additional technical information at the end of this
data sheet.
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysIO buffers as shown in Figure 2-25. The PIO Block
supplies the output data (DO) and the tri-state control signal (TO) to the sysIO buffer and receives input from the
buffer. Figure 2-12 provides the PIO signal list.
Figure 2-25. PIC Diagram
DDRCLKPOL*
*Signals are available on left/right/bottom edges only.
** Selected blocks.
DQSXFER*
QNEG0*
QNEG1*
ONEG2*
QPOS0*
QPOS1*
OPOS2*
OPOS0
ONEG0
ONEG1
OPOS1
INCK**
INDD
ECLK1
ECLK2
IPOS0
IPOS1
GSRN
INFF
CLK
LSR
CE
TD
ECP2-12
ECP2-20
ECP2-35
ECP2-50
ECP2-70
ECP2-6
Device
Control
Muxes
CLK1
CLK0
CEO
GSR
LSR
CEI
DSP Block
2-27
18
22
3
6
7
8
Shared Resources
PIOA
Register
Register
Register
Tristate
Output
Block
Block
Block
Input
PIOB
IOLD0
IOLT0
DI
DSP Performance
LatticeECP2 Family Data Sheet
MMAC
TBA
TBA
TBA
TBA
TBA
TBA
Buffer
sysIO
PADB
PADA
“C”
“T”
Architecture