KSZ8841-16MVLI TR Micrel, KSZ8841-16MVLI TR Datasheet - Page 34

• Manufacturer Part Number: KSZ8841-16MVLI TR
• Description: Ethernet ICs Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free)
• Manufacturer: Micrel

Specifications of KSZ8841-16MVLI TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-128
• Mounting Style: SMD/SMT

October 2007
Micrel, Inc.
Signal
Common Signals
A[15:1]
AEN
BE3N, BE2N,
BE1N, BE0N
D[31:16]
D[15:0]
ADSN
LDEVN
DATACSN
INTR
Synchronous Transfer Signals
VLBUSN
CYCLEN
SWR
SRDYN
RDYRTNN
Type
I
I
I
I/O
I/O
I
O
I
O
I
I
I
O
I
(1)
Function
Address
Address Enable
Address Enable asserted indicates memory address on the bus for DMA access
and since the device is an I/O device, address decoding is only enabled when AEN
is Low.
Byte Enable
Note 1: BE3N, BE2N, BE1N and BE0N are ignored when DATACSN is low because
32 bit transfers are assumed.
Note 2: BE2N and BE3N are valid only for the KSZ8841-32 mode, and are No
Connect for the KSZ8841-16 mode.
Data
For KSZ8841M-32 mode only.
Data
For both KSZ8841-32 and KSZ8841-16 Modes
Address Strobe
The rising edge of ADSN is used to latch A[15:1], AEN, BE3N, BE2N, BE1N and
BE0N.
Local Device
This signal is a combinatorial decode of AEN and A[15:4]. This A[15:4] is used to
compare against the Base Address Register.
Data Register Chip Select (For KSZ8841-32MQL Mode only)
This signal is used for central decoding architecture (mostly for embedded
application). When asserted, the device’s local decoding logic is ignored and the 32-
bit access to QMU Data Register is assumed.
Interrupt
VLBUS
VLBUSN = 0, VLBus-like cycle.
VLBUSN = 1, burst cycle (both host/system and KSZ8841M can insert wait state)
CYCLEN
For VLBus-like access: used to sample SWR when asserted.
For burst access: used to connect to IOWC# bus signal to indicate burst write.
Write/Read
For VLBus-like access: used to indicate write (High) or read (Low) transfer.
For burst access: used to connect to IORC# bus signal to indicate burst read.
Synchronous Ready
For VLBus-like access: exactly the same signal definition of nSRDY in VLBus.
For burst access: insert wait state by KSZ8841M whenever necessary during the
Data Register access.
Ready Return
For VLBus-like access: exactly like RDYRTNN signal in VLBus to end the cycle.
BE0N
0
0
1
0
1
1
1
BE1N
0
0
1
1
0
1
1
34
BE2N
0
1
0
1
1
0
1
BE3N
0
1
0
1
1
1
0
Higher 16-bit (D[31:16]) access
Byte 2 (D[23:16]) access
Byte 3 (D[31:24]) access
Description
32-bit access
Lower 16-bit (D[15:0]) access
Byte 0 (D[7:0]) access
Byte 1 (D[15:8]) access
KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6