KSZ8841-16MVLI TR Micrel, KSZ8841-16MVLI TR Datasheet - Page 68

• Manufacturer Part Number: KSZ8841-16MVLI TR
• Description: Ethernet ICs Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free)
• Manufacturer: Micrel

Specifications of KSZ8841-16MVLI TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-128
• Mounting Style: SMD/SMT

Bank 18 Interrupt Enable Register (0x00): IER
This register enables the interrupts from the QMU and other sources.
October 2007
Micrel, Inc.
Bit
15
14
13
12
11
10
9
8
7
6-0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
-
Default Value
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
Description
LCIE Link Change Interrupt Enable
When this bit is set, the link change interrupt is enabled.
When this bit is reset, the link change interrupt is disabled.
TXIE Transmit Interrupt Enable
When this bit is set, the transmit interrupt is enabled.
When this bit is reset, the transmit interrupt is disabled.
RXIE Receive Interrupt Enable
When this bit is set, the receive interrupt is enabled.
When this bit is reset, the receive interrupt is disabled.
TXUIE Transmit Underrun Interrupt Enable
When this bit is set, the transmit underrun interrupt is enabled.
When this bit is reset, the transmit underrun interrupt is disabled.
RXOIE Receive Overrun Interrupt Enable
When this bit is set, the Receive Overrun interrupt is enabled.
When this bit is reset, the Receive Overrun interrupt is disabled.
RXEIE Receive Early Receive Interrupt Enable
When this bit is set, the Early Receive interrupt is enabled.
When this bit is reset, the Early Receive interrupt is disabled.
TXPSIE Transmit Process Stopped Interrupt Enable
When this bit is set, the Transmit Process Stopped interrupt is enabled.
When this bit is reset, the Transmit Process Stopped interrupt is disabled.
RXPSIE Receive Process Stopped Interrupt Enable
When this bit is set, the Receive Process Stopped interrupt is enabled.
When this bit is reset, the Receive Process Stopped interrupt is disabled.
RXEFIE Receive Error Frame Interrupt Enable
When this bit is set, the Receive error frame interrupt is enabled.
When this bit is reset, the Receive error frame interrupt is disabled.
Reserved.
68
KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6