KSZ8841-16MVLI TR Micrel, KSZ8841-16MVLI TR Datasheet - Page 69

• Manufacturer Part Number: KSZ8841-16MVLI TR
• Description: Ethernet ICs Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free)
• Manufacturer: Micrel

Specifications of KSZ8841-16MVLI TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-128
• Mounting Style: SMD/SMT

Bank 18 Interrupt Status Register (0x02): ISR
This register contains the status bits for all QMU and other interrupt sources.
When the corresponding enable bit is set, it causes the interrupt pin to be asserted.
This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register
bits are not cleared when read. The user has to write “1” to clear
October 2007
Micrel, Inc.
Bit
15
14
13
12
11
10
9
8
7
6-0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x1
0x0
-
Default Value
R/W
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
Description
LCIS Link Change Interrupt Status
When this bit is set, it indicates that the link status has changed from link up to link down, or
link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
TXIS Transmit Status
When this bit is set, it indicates that the TXQ MAC has transmitted at least a frame on the
MAC interface and the QMU TXQ is ready for new frames from the host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXIS Receive Interrupt Status
When this bit is set, it indicates that the QMU RXQ has received a frame from the MAC
interface and the frame is ready for the host CPU to process.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
TXUIS Transmit Underrun Interrupt Status
When this bit is set, it indicates that the transmit underrun condition has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXOIS Receive Overrun Interrupt Status
When this bit is set, it indicates that the Receive Overrun status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXEIS Receive Early Receive Interrupt Status
When this bit is set, it indicates that the Early Receive status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
TXPSIE Transmit Process Stopped Status
When this bit is set, it indicates that the Transmit Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXPSIE Receive Process Stopped Status
When this bit is set, it indicates that the Receive Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXEFIE Receive Error Frame Interrupt Status
When this bit is set, it indicates that the Receive error frame status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved.
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KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6