KSZ8841-16MVLI TR Micrel, KSZ8841-16MVLI TR Datasheet - Page 67

• Manufacturer Part Number: KSZ8841-16MVLI TR
• Description: Ethernet ICs Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free)
• Manufacturer: Micrel

Specifications of KSZ8841-16MVLI TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-128
• Mounting Style: SMD/SMT

Bank 17 QMU Data Register Low (0x08): QDRL
This register QDRL(0x08-0x09) contains the Low data word presently addressed by the pointer register. Reading maps
from the RXQ, and writing maps to the TXQ.
Bank 17 QMU Data Register High (0x0A): QDRH
This register QDRH(0x0A-0x0B) contains the High data word presently addressed by the pointer register. Reading maps
from the RXQ, and writing maps to the TXQ.
October 2007
Micrel, Inc.
Bit
15-0
Bit
15-0
-
-
Default Value
Default Value
R/W
RW
R/W
RW
Description
QDRL Queue Data Register Low
This register is mapped into two uni-directional buffers for 16-bit buses, and one uni-directional
buffer for 32-bit buses, (TXQ when Write, RXQ when Read) that allow moving words to and
from the KSZ8841M regardless of whether the pointer is even, odd, or Dword aligned. Byte,
word, and Dword access can be mixed on the fly in any order. This register along with DQRH
is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit
buses, to facilitate Dword move operations.
Description
QDRL Queue Data Register High
This register is mapped into two uni-directional buffers for 16-bit buses, and one uni-directional
buffer for 32-bit buses, (TXQ when Write, RXQ when Read) that allow moving words to and
from the KSZ8841M regardless of whether the pointer is even, odd, or dword aligned. Byte,
word, and Dword access can be mixed on the fly in any order. This register along with DQRL
is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit
buses, to facilitate Dword move operations.
67
KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6