KSZ8841-16MVLI TR Micrel, KSZ8841-16MVLI TR Datasheet - Page 43
![no-image](/images/no-image-200.jpg)
KSZ8841-16MVLI TR
Manufacturer Part Number
KSZ8841-16MVLI TR
Description
Ethernet ICs Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free)
Manufacturer
Micrel
Datasheet
1.KSZ8841-16MVL_TR.pdf
(105 pages)
Specifications of KSZ8841-16MVLI TR
Rohs
yes
Product
Ethernet Controllers
Package / Case
LQFP-128
Mounting Style
SMD/SMT
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Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
CPU Interface I/O Registers
The KSZ8841M provides an EISA-like, ISA-like, or VLBUS-like bus interface for the CPU to access its internal I/O
registers. I/O registers serve as the address that the microprocessor uses when communicating with the device. This is
used for configuring operational settings, reading or writing control, status information, and transferring packets by reading
and writing through the packet data registers.
I/O Registers
Input/Output (I/O) registers are limited to 16 locations as required by most ISA bus-based systems; therefore, registers
are assigned to different banks. The last word of the I/O register locations (0xE - 0xF) is shared by all banks and can be
used to change the bank in use.
The following I/O Space Mapping Tables apply to 8, 16 or 32-bit bus products. Depending upon the bus interface used
and byte enable signals (BE[3:0]N control byte access), each I/O access can be performed as an 8-bit, 16-bit, or 32-bit
operation. (The KSZ8841M is not limited to 8/16-bit performance and 32-bit read/write are also supported).
October 2007
43
M9999-102207-1.6
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