KSZ8841-16MVLI TR Micrel, KSZ8841-16MVLI TR Datasheet - Page 71

• Manufacturer Part Number: KSZ8841-16MVLI TR
• Description: Ethernet ICs Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free)
• Manufacturer: Micrel

Specifications of KSZ8841-16MVLI TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-128
• Mounting Style: SMD/SMT

Bank 18 Early Transmit Register (0x08): ETXR
This register specifies the threshold for the early transmit.
Bank 18 Early Receive Register (0x0A): ERXR
This register specify the threshold for early receive and interrupt condition.
Bank 19 Multicast Table Register 0 (0x00): MTR0
The 64-bit multicast table is used for group address filtering. This value is defined as the six most significant bits from
CRC circuit calculation result that is based on 48-bit of DA input. The two most significant bits select one of the four
registers to be used, while the others determine which bit within the register.
Multicast table register 0.
October 2007
Micrel, Inc.
Bit
15-8
7
6-5
4-0
Bit
15-8
7
6-5
4-0
Bit
15-0
-
0x0
-
-
0x0
-
Default Value
0x00
Default Value
0x1F
Default Value
0x0
R/W
RO
RW
RO
RW
R/W
RO
RW
RO
RW
R/W
RW
Description
Reserved.
TXEE Early Transmit Enable
When this bit is set, the Early Transmit function is enabled.
When this bit is cleared, normal operation is assumed.
Reserved.
ETXTH Early Transmit Threshold
The threshold for Early Transmit. Specified in unit of 64-byte. Whenever the number of bytes
written in memory for the presently transmitting packet exceeds the threshold, Early Transmit
will be started on the network interface.
When early transmit is enabled, setting this field to 0 is invalid, and the hardware behavior is
unknown.
Description
Reserved.
RXEE Early Receive Enable
When this bit is set, the Early Receive function is enabled.
When this bit is cleared, normal operation is assumed.
Reserved.
ERXTH Early Receive Threshold
The threshold for Early Receive and Interrupt. Specified in unit of 64-byte. Whenever the
number of bytes written in memory for the presently received packet exceeds the threshold,
early receive status will be set, and Early Receive interrupt will be asserted if its interrupt is
enabled.
When early receive is enabled, setting this field to 0 is invalid, and the hardware behavior is
unknown.
Description
MTR0 Multicast Table 0
When the appropriate bit is set, if the packet received with DA matches the CRC, the hashing
function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all
multicast addresses are received regardless of the multicast table value.
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KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6