KSZ8841-16MVLI TR Micrel, KSZ8841-16MVLI TR Datasheet - Page 36

• Manufacturer Part Number: KSZ8841-16MVLI TR
• Description: Ethernet ICs Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free)
• Manufacturer: Micrel

Specifications of KSZ8841-16MVLI TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-128
• Mounting Style: SMD/SMT

Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
Synchronous Interface
For synchronous transfers, the synchronous dedicated signals CYCLEN, SWR, and RDYRTNN will toggle but the
asynchronous dedicated signals RDN and WRN are de-asserted and stay at the same logic level throughout the entire
synchronous transfer.
The synchronous interface mainly supports two applications, one for VLBus-like and the other for EISA-like (DMA type C)
burst transfers. The VLBus-like interface supports only single-data transfer. The pin option VLBUSN determines if it is a
VLBus-like or EISA-like burst transfer – if VLBUSN = 0, the interface is for VLBus-like transfer; if VLBUSN = 1, the
interface is for EISA-like burst transfer.
For VLBus-like transfer interface (VLBUSN = 0):
This interface is used in an architecture in which the device’s local decoder is utilized; that is, the BIU decodes latched
A[15:4] and qualifies with AEN (Address Enable) to determine if the KSZ8841M device is the intended target. No burst is
supported in this application. The M/nIO signal connection in VLBus is routed to AEN. The CYCLEN in this application is
used to sample the SWR signal when it is asserted. Usually, CYCLEN is one clock delay of ADSN. There is a
handshaking process to end the cycle of VLBus-like transfers. When the KSZ8841M is ready to finish the cycle, it asserts
.
SRDYN
The system/host acknowledges SRDYN by asserting RDYRTNN after the system/host has latched the read
data. The KSZ8841M holds the read data until RDYRTNN is asserted. The timing waveform is shown in Figures 19 and
20.
For EISA-like burst transfer interface (VLBUSN = 1):
The SWR is connected to IORC# in EISA to indicate the burst read and CYCLEN is connected to IOWC# in EISA to
indicate the burst write. Note that in this application, both the system/host/memory and KSZ8841M are capable of
inserting wait states. For system/host/memory to insert a wait state, assert the RDYRTNN signal; for the KSZ8841M to
insert the wait state, assert the SRDYN signal. The timing waveform is shown in Figures 17 and 18.
BIU Summation
Figure 10 shows the mapping from ISA-like, EISA-like and VLBus-like transactions to the chip’s BIU.
Figure 11 shows the connection for different data bus sizes.
Note: For the 8-bit data bus mode, the internal inverter is enabled and connected between BE0N and BE1N, so an even
address will enable the BE0N and an odd address will enable the BE1N.
October 2007
36
M9999-102207-1.6