KSZ8841-16MVLI TR Micrel, KSZ8841-16MVLI TR Datasheet - Page 8

• Manufacturer Part Number: KSZ8841-16MVLI TR
• Description: Ethernet ICs Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free)
• Manufacturer: Micrel

Specifications of KSZ8841-16MVLI TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-128
• Mounting Style: SMD/SMT

Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
List of Figures
Figure 1. KSZ8841M Functional Diagram............................................................................................................................... 1
Figure 2. Standard – KSZ8841-16MQL 128-Pin PQFP ........................................................................................................ 10
Figure 3. Option – KSZ8841-16MVL 128-Pin LQFP............................................................................................................. 10
Figure 4. KSZ8841-16MBL 100-Ball LFBGA (Top View)...................................................................................................... 11
Figure 5. Standard – KSZ8841-32MQL 128-Pin PQFP ........................................................................................................ 21
Figure 6. Option – KSZ8841-32MVL 128-Pin LQFP............................................................................................................. 21
Figure 7. Typical Straight Cable Connection ........................................................................................................................ 30
Figure 8. Typical Crossover Cable Connection .................................................................................................................... 30
Figure 9. Auto Negotiation and Parallel Operation ............................................................................................................... 31
Figure 10. Mapping from the ISA, EISA, and VLBus to the KSZ8841M Bus Interface......................................................... 37
Figure 11. KSZ8841M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections................................................................................ 37
Figure 12. PHY Port 1 Near-end (Remote) Loopback Path.................................................................................................. 42
Figure 13. Asynchronous Cycle – ADSN = 0 ........................................................................................................................ 89
Figure 14. Asynchronous Cycle – Using ADSN.................................................................................................................... 90
Figure 15. Asynchronous Cycle – Using DATACSN............................................................................................................. 91
Figure 16. Address Latching Cycle for All Modes ................................................................................................................. 92
Figure 17. Synchronous Burst Write Cycles – VLBUSN = 1................................................................................................. 93
Figure 18. Synchronous Burst Read Cycles – VLBUSN = 1 ................................................................................................ 94
Figure 19. Synchronous Write Cycle – VLBUSN = 0............................................................................................................ 95
Figure 20. Synchronous Read Cycle – VLBUSN = 0............................................................................................................ 96
Figure 21. Auto Negotiation Timing....................................................................................................................................... 97
Figure 22. Reset Timing........................................................................................................................................................ 98
Figure 23. EEPROM Read Cycle Timing Diagram .............................................................................................................. 99
Figure 24. 128-Pin PQFP Package..................................................................................................................................... 101
Figure 25. Optional 128-Pin LQFP Package....................................................................................................................... 102
Figure 26. Optional 100-Ball LFBGA Package ................................................................................................................... 103
October 2007
8
M9999-102207-1.6