S9S08SG8E2VTG Freescale Semiconductor, S9S08SG8E2VTG Datasheet - Page 109

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S9S08SG8E2VTG

Manufacturer Part Number
S9S08SG8E2VTG
Description
8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S08SG8E2VTG

Rohs
yes
Core
S08
Processor Series
MC9S08SG8
Data Bus Width
8 bit
Maximum Clock Frequency
40 MHz
Program Memory Size
8 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
TSSOP-16
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
12
Interface Type
SCI, SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
2.7 V
Freescale Semiconductor
RSP
RTI
RTS
SBC #opr8i
SBC opr8a
SBC opr16a
SBC oprx16,X
SBC oprx8,X
SBC ,X
SBC oprx16,SP
SBC oprx8,SP
SEC
SEI
STA opr8a
STA opr16a
STA oprx16,X
STA oprx8,X
STA ,X
STA oprx16,SP
STA oprx8,SP
STHX opr8a
STHX opr16a
STHX oprx8,SP
STOP
STX opr8a
STX opr16a
STX oprx16,X
STX oprx8,X
STX ,X
STX oprx16,SP
STX oprx8,SP
Source
Form
Reset Stack Pointer (Low Byte)
SPL  0xFF
(High Byte Not Affected)
Return from Interrupt
SP  (SP) + 0x0001; Pull (CCR)
SP  (SP) + 0x0001; Pull (A)
SP  (SP) + 0x0001; Pull (X)
SP  (SP) + 0x0001; Pull (PCH)
SP  (SP) + 0x0001; Pull (PCL)
Return from Subroutine
SP  SP + 0x0001PullPCH)
SP  SP + 0x0001; Pull (PCL)
Subtract with Carry
A  (A) – (M) – (C)
Set Carry Bit
(C  1)
Set Interrupt Mask Bit
(I  1)
Store Accumulator in Memory
M (A)
Store H:X (Index Reg.)
(M:M + 0x0001)  (H:X)
Enable Interrupts: Stop Processing
Refer to MCU Documentation
I bit  0; Stop Processing
Store X (Low 8 Bits of Index Register)
in Memory
M (X)
Table 7-2. Instruction Set Summary (Sheet 7 of 9)
Operation
MC9S08SG8 MCU Series Data Sheet, Rev. 7
INH
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
INH
INH
DIR
EXT
IX2
IX1
IX
SP2
SP1
DIR
EXT
SP1
INH
DIR
EXT
IX2
IX1
IX
SP2
SP1
Object Code
9E D2
9E E2
9E D7
9E E7
9E FF
9E DF
9E EF
9C
80
81
A2
B2
C2
D2
E2
F2
99
9B
B7
C7
D7
E7
F7
35
96
8E
BF
CF
DF
EF
FF
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
hh ll
ee ff
ff
ee ff
ff
dd
hh ll
ff
dd
hh ll
ee ff
ff
ee ff
ff
Chapter 7 Central Processor Unit (S08CPUV2)
1
9
5
2
3
4
4
3
3
5
4
1
1
3
4
4
3
2
5
4
4
5
5
2
3
4
4
3
2
5
4
p
uuuuufppp
ufppp
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
p
p
wpp
pwpp
pwpp
wpp
wp
ppwpp
pwpp
wwpp
pwwpp
pwwpp
fp...
wpp
pwpp
pwpp
wpp
wp
ppwpp
pwpp
Cyc-by-Cyc
Details
VH I N Z C
– – – – – –
– – – – – –
– – – – – 1
– – 1 – – –
0 –
0 –
– – 0 – – –
0 –
–
 
on CCR
Affect
– 
–  –
–  –
–  –
105

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