S9S08SG8E2VTG Freescale Semiconductor, S9S08SG8E2VTG Datasheet - Page 132

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S9S08SG8E2VTG

Manufacturer Part Number
S9S08SG8E2VTG
Description
8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S08SG8E2VTG

Rohs
yes
Core
S08
Processor Series
MC9S08SG8
Data Bus Width
8 bit
Maximum Clock Frequency
40 MHz
Program Memory Size
8 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
TSSOP-16
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
12
Interface Type
SCI, SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
2.7 V
Analog-to-Digital Converter (S08ADCV1)
9.3.3
ADCRH contains the upper two bits of the result of a 10-bit conversion. When configured for 8-bit
conversions both ADR8 and ADR9 are equal to zero. ADCRH is updated each time a conversion
completes except when automatic compare is enabled and the compare condition is not met. In 10-bit
MODE, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result
registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, then the
intermediate conversion result will be lost. In 8-bit mode there is no interlocking with ADCRL. In the case
that the MODE bits are changed, any data in ADCRH becomes invalid.
9.3.4
ADCRL contains the lower eight bits of the result of a 10-bit conversion, and all eight bits of an 8-bit
conversion. This register is updated each time a conversion completes except when automatic compare is
enabled and the compare condition is not met. In 10-bit mode, reading ADCRH prevents the ADC from
transferring subsequent conversion results into the result registers until ADCRL is read. If ADCRL is not
read until the after next conversion is completed, then the intermediate conversion results will be lost. In
8-bit mode, there is no interlocking with ADCRH. In the case that the MODE bits are changed, any data
in ADCRL becomes invalid.
128
ACFGT
ACFE
Field
5
4
Reset:
W
R
Data Result High Register (ADCRH)
Data Result Low Register (ADCRL)
Compare Function Enable — ACFE is used to enable the compare function.
0 Compare function disabled
1 Compare function enabled
Compare Function Greater Than Enable — ACFGT is used to configure the compare function to trigger when
the result of the conversion of the input being monitored is greater than or equal to the compare value. The
compare function defaults to triggering when the result of the compare of the input being monitored is less than
the compare value.
0 Compare triggers when input is less than compare level
1 Compare triggers when input is greater than or equal to compare level
7
0
0
Table 9-4. ADCSC2 Register Field Descriptions (continued)
= Unimplemented or Reserved
Figure 9-6. Data Result High Register (ADCRH)
0
0
6
MC9S08SG8 MCU Series Data Sheet, Rev. 7
0
0
5
0
0
4
Description
0
0
3
0
0
2
ADR9
Freescale Semiconductor
0
1
ADR8
0
0

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