S9S08SG8E2VTG Freescale Semiconductor, S9S08SG8E2VTG Datasheet - Page 255

• Manufacturer Part Number: S9S08SG8E2VTG
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTG

• Rohs: yes
• Core: S08
• Processor Series: MC9S08SG8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TSSOP-16
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

16.3.5
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel registers are cleared by
reset.
Freescale Semiconductor
ELSnB
ELSnA
MSnA
Field
3–2
4
Mode select A for TPM channel n. When CPWMS=0 and MSnB=0, MSnA configures TPM channel n for
input-capture mode or output compare mode. Refer to
controls.
Note: If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
Edge/level select bits. Depending upon the operating mode for the timer channel as set by CPWMS:MSnB:MSnA
and shown in
the level that will be driven in response to an output compare match, or select the polarity of the PWM output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general purpose I/O pin not related to any timer
functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin
available as a general purpose I/O pin when the associated timer channel is set up as a software timer that does
not require the use of a pin.
TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)
CPWMS
X
0
1
mode, it is possible to get an unexpected indication of an edge trigger.
Table
MSnB:MSnA
Table 16-8. TPMxCnSC Field Descriptions (continued)
16-9, these bits select the polarity of the input edge that triggers an input capture event, select
XX
XX
1X
00
01
Table 16-9. Mode, Edge, and Level Selection
MC9S08SG8 MCU Series Data Sheet, Rev. 7
ELSnB:ELSnA
X1
X1
00
01
10
11
01
10
11
10
10
Description
Output compare
Center-aligned
Edge-aligned
Table 16-9
Input capture
Pin not used for TPM - revert to general
purpose I/O or other peripheral control
Mode
PWM
PWM
for a summary of channel mode and setup
Capture on falling edge
Capture on rising edge
Set output on compare
High-true pulses (clear
High-true pulses (clear
output on compare-up)
output on compare-up)
Low-true pulses (set
Low-true pulses (set
Capture on rising or
output on compare)
output on compare)
Toggle output on
Clear output on
Configuration
falling edge
compare
compare
Timer/PWM Module (S08TPMV3)
only
only
251