S9S08SG8E2VTG Freescale Semiconductor, S9S08SG8E2VTG Datasheet - Page 78

• Manufacturer Part Number: S9S08SG8E2VTG
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTG

• Rohs: yes
• Core: S08
• Processor Series: MC9S08SG8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TSSOP-16
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

Chapter 5 Resets, Interrupts, and General System Control
5.7.7
This register is used to report the status of the low voltage warning function, and to configure the stop
mode behavior of the MCU.
74
1
2
Any other Reset:
Power-on Reset:
PPDACK
This bit can be written only one time after power-on reset. Additional writes are ignored.
This bit can be written only one time after reset. Additional writes are ignored.
PPDC
LVWV
PPDF
Field
LVDV
LVD Reset:
5
4
3
2
0
System Power Management Status and Control 2 Register
(SPMSC2)
Low-Voltage Detect Voltage Select — This write-once bit selects the low voltage detect (LVD) trip point setting.
It also selects the warning voltage range. See
Low-Voltage Warning Voltage Select — This bit selects the low voltage warning (LVW) trip point voltage. See
Table
Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit
Partial Power Down Control — This write-once bit controls whether stop2 or stop3 mode is selected.
0 Stop3 mode enabled.
1 Stop2, partial power down, mode enabled.
Figure 5-9. System Power Management Status and Control 2 Register (SPMSC2)
W
R
1
5-11.
See Electrical Characteristics appendix for minimum and maximum values.
0
0
0
0
7
LVDV:LVWV
0:0
0:1
1:0
1:1
= Unimplemented or Reserved
Table 5-11. LVD and LVW trip point typical values
Table 5-10. SPMSC2 Register Field Descriptions
0
0
0
0
6
MC9S08SG8 MCU Series Data Sheet, Rev. 7
LVDV
0
u
u
5
LVW Trip Point
V
V
V
V
LVW0
LVW1
1
LVW2
LVW3
= 2.74 V
= 2.92 V
= 4.3 V
= 4.6 V
LVWV
Table
4
0
u
u
Description
5-11.
PPDF
0
0
0
3
LVD Trip Point
V
V
LVD0
LVD1
PPDACK
u = Unaffected by reset
= 2.56 V
= 4.0 V
0
0
0
0
2
1
Freescale Semiconductor
0
0
0
0
1
PPDC
0
0
0
0
2