S9S08SG8E2VTG Freescale Semiconductor, S9S08SG8E2VTG Datasheet - Page 241

• Manufacturer Part Number: S9S08SG8E2VTG
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTG

• Rohs: yes
• Core: S08
• Processor Series: MC9S08SG8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TSSOP-16
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

Freescale Semiconductor
Write to TPMxCnTH:L registers
Any write to TPMxCNTH or TPMxCNTL registers
Read of TPMxCNTH:L registers
In BDM mode, any read of TPMxCNTH:L registers
In BDM mode, a write to TPMxSC, TPMxCNTH or TPMxCNTL Clears this read coherency
Read of TPMxCnVH:L registers
In BDM mode, any read of TPMxCnVH:L registers
In BDM mode, a write to TPMxCnSC
Write to TPMxCnVH:L registers
In Input Capture mode, writes to TPMxCnVH:L registers
In Output Compare mode, when (CLKSB:CLKSA not = 0:0),
writes to TPMxCnVH:L registers
In Edge-Aligned PWM mode when (CLKSB:CLKSA not = 00),
writes to TPMxCnVH:L registers
Action
Table 16-2. TPMV2 and TPMV3 Porting Considerations
3
1
1
2
MC9S08SG8 MCU Series Data Sheet, Rev. 7
3
Clears the TPM counter
(TPMxCNTH:L) and the
prescaler counter.
Returns the value of the TPM
counter that is frozen.
mechanism.
Returns the value of the
TPMxCnVH:L register.
Clears this read coherency
mechanism.
Not allowed.
Update the TPMxCnVH:L
registers with the value of
their write buffer at the next
change of the TPM counter
(end of the prescaler
counting) after the second
byte is written.
Update the TPMxCnVH:L
registers with the value of
their write buffer after both
bytes were written and when
the TPM counter changes
from (TPMxMODH:L - 1) to
(TPMxMODH:L).
Note: If the TPM counter is a
free-running counter, then
this update is made when the
TPM counter changes from
0xFFFE to 0xFFFF.
TPMV3
Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)
Clears the TPM counter
(TPMxCNTH:L) only.
If only one byte of the
TPMxCNTH:L registers was
read before the BDM mode
became active, returns the
latched value of TPMxCNTH:L
from the read buffer (instead of
the frozen TPM counter value).
Does not clear this read
coherency mechanism.
If only one byte of the
TPMxCnVH:L registers was
read before the BDM mode
became active, returns the
latched value of TPMxCNTH:L
from the read buffer (instead of
the value in the TPMxCnVH:L
registers).
Does not clear this read
coherency mechanism.
Allowed.
Always update these registers
when their second byte is
written.
Update after both bytes are
written and when the TPM
counter changes from
TPMxMODH:L to 0x0000.
TPMV2
237