S9S08SG8E2VTG Freescale Semiconductor, S9S08SG8E2VTG Datasheet - Page 312

• Manufacturer Part Number: S9S08SG8E2VTG
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTG

• Rohs: yes
• Core: S08
• Processor Series: MC9S08SG8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TSSOP-16
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

Appendix A Electrical Characteristics
A.12.3
Table A-15
308
1
2
3
4
5
6
Num
Electrical characteristics only apply to the temperature rated devices marked with x.
Maximum baud rate must be limited to 5 MHz due to input filter characteristics.
Refer to
All timing is shown with respect to 20% V
rate control disabled and high drive strength enabled for SPI output pins.
Time to data active from high-impedance state.
Hold time to high-impedance state.
10
11
12
1
2
3
4
5
6
7
8
9
1
Figure A-14
D
D
D
D
D
D
D
D
D
D
D
D
C
and
SPI
Cycle time
Enable lead time
Enable lag time
Clock (SPSCK) high time
Clock (SPSCK) low time
Data setup time (inputs)
Data hold time (inputs)
Access time, slave
Disable time, slave
Data setup time (outputs)
Data hold time (outputs)
Operating frequency
Figure A-14
through
Rating
Master and Slave
Master and Slave
Figure
through
4
5
2
A-17.
Table A-15. SPI Electrical Characteristic
MC9S08SG8 MCU Series Data Sheet, Rev. 7
Master
Master
Master
Master
Master
Master
Master
Master
DD
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Figure A-17
and 70% V
Symbol
t
t
t
t
t
t
t
t
SCKH
t
t
SCKL
HI(M)
t
t
SI(M)
Lead
Lead
SI(S)
HI(S)
t
t
t
t
t
SCK
SCK
f
f
Lag
Lag
HO
HO
t
SO
SO
dis
op
op
A
DD
, unless noted; 100 pF load on all SPI pins. All timing assumes slew
describe the timing requirements for the SPI system.
1/2 t
1/2 t
f
Bus
SCK
SCK
–10
–10
Min
1/2
1/2
dc
30
30
30
30
25
25
—
—
—
/2048
2
4
0
– 25
– 25
f
2048
Bus
Max
1/2
1/2
—
—
—
40
40
5
—
—
—
—
—
—
—
—
—
—
6
/4
t
t
t
t
MHz
Unit
t
t
SCK
SCK
SCK
SCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
Freescale Semiconductor
Standard
x
x
x
x
x
x
x
x
x
x
x
x
Temp Rated
AEC Grade
3
0
x
x
x
x
x
x
x
x
x
x
x
x