XRT83L34ES Exar, XRT83L34ES Datasheet - Page 24

• Manufacturer Part Number: XRT83L34ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L34ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83L34
REV. 1.0.1
ALARM FUNCTION//REDUNDANCY SUPPORT
S
S
MCLKOUT
IGNAL
IGNAL
MCLKT1
GAUGE
DMO_0
DMO_1
DMO_2
DMO_3
ATAOS
N
N
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
AME
AME
P
P
33
36
87
64
65
66
67
50
IN
IN
#
#
T
T
YPE
YPE
O
O
I
I
I
T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with required
accuracy of better than ±50ppm and duty cycle of 40% to 60%. MCLKT1
input is used in the T1 mode.
N
Synthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1
or E1 rate based upon the mode of operation.
Twisted Pair Cable Wire Gauge Select - Hardware mode
Connect this pin "High" to select 26 Gauge wire. Connect this pin “Low” to
select 22 and 24 gauge wire for all channels.
N
Driver Failure Monitor Channel _0
This pin transitions "High" if a short circuit condition is detected in the trans-
mit driver of Channel _0, or no transmit output pulse is detected for more
than 128 TCLK_0 cycles.
Driver Failure Monitor Channel _1
Driver Failure Monitor Channel _2
Driver Failure Monitor Channel _3
Automatic Transmit “All Ones” Pattern - Hardware Mode Only:
A "High" level on this pin enables the automatic transmission of an "All Ones"
AMI pattern from the transmitter of any channel that the receiver of that chan-
nel has detected an LOS condition. A "Low" level on this pin disables this
function.
N
Microprocessor Clock Input - Host Mode
This pin should be tied to GND for asynchronous microprocessor modes.
N
OTES
OTE
OTE
OTE
1. All channels of the XRT83L34 must be operated at the same clock
2. See pin 32 description for further explanation for the usage of this
3. Internally pulled “Low” with a 50kΩ resistor.
: Internally pulled “Low” with a 50kΩ resistor.
: All channels share the same ATAOS input control function.
: This pin is internally pulled “Low” for asynchronous microprocessor
:
interface when no clock is present.
rate, either T1, E1 or J1.
pin.
21
D
D
ESCRIPTION
ESCRIPTION
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