XRT83L34ES Exar, XRT83L34ES Datasheet - Page 62

• Manufacturer Part Number: XRT83L34ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L34ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83L34
REV. 1.0.1
N
Figure _ presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals, during a "Motorola-
Asynchronous" Write Operation.
F
8. After waiting the appropriate time for the data (on the bi-directional data bus) to settle and can be safely
9. After the Microprocessor detects the RDY*/DTACK* signal (from the XRT83L34 device) toggling "LOW", it
1. The XRT83L34 device will latch the contents of the bi-directional data bus into the Microprocessor Inter-
2. The XRT83L34 device will terminate the "WRITE" cycle.
OTE
IGURE
accepted by the Microprocessor, the XRT83L34 device will indicate that this data can now be latched into
the "target" address location by toggling the "RDY*/DTACK*" output pin "LOW.
can then terminate the WRITE cycle by toggling the "RD*/DS*" (Data Strobe) input pin "HIGH".
face block.
: Once the user toggles the "RD*/DS* (Data Strobe) input pin "HIGH", then the following two things will happen.
28. I
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
LLUSTRATION OF A
RD*/DS*
A[6:0]
ALE/AS*
WR/R/W*
RDY*/DTACK*
D[7:0]
CS*
Address Decoding
Circuitry asserts
CS*
Microprocessor toggles “R/W*” low
To Denote WRITE operation
Microprocessor places “target”
Address value on A[6:0]
M
OTOROLA
Write Operation begins
Here
-A
SYNCHRONOUS
Address of Target Register
Data to be Written
DTACK* toggles “low” to indicate
That valid data can be latched into
“target” Address location of chip
59
W
RITE
O
PERATION
Write Operation is
Terminated Here
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