XRT83L34ES Exar, XRT83L34ES Datasheet - Page 40

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XRT83L34ES

Manufacturer Part Number
XRT83L34ES
Description
Peripheral Drivers & Components - PCIs
Manufacturer
Exar
Datasheet

Specifications of XRT83L34ES

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
XRT83L34
REV. 1.0.1
Figure 14
simplified diagram for E1 (75Ω) in the external receive termination mode.
RXTSEL
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
is a simplified diagram for T1 (100Ω) in the external receive termination mode.
F
IGURE
TERSEL1
x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
14. S
IMPLIFIED
TERSEL0
X R T 8 3 L 3 4 L IU
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D
IAGRAM FOR
T R IN G
R R IN G
T
T T IP
R T IP
ABLE
RXRES1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
7: R
1 0 0
T1
ECEIVE
IN THE
3 .1
3 .1
37
RXRES0
T
ERMINATIONS
x
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
E
XTERNAL
1 :2 .4 5
1 :1
240Ω
240Ω
240Ω
240Ω
210Ω
210Ω
210Ω
210Ω
150Ω
150Ω
150Ω
150Ω
T
R
R
ERMINATION
ext
ext
1 0 0
1 0 0
M
100Ω
120Ω
172Ω
204Ω
108Ω
240Ω
192Ω
232Ω
280Ω
300Ω
412Ω
150Ω
600Ω
110Ω
116Ω
75Ω
R
ODE
int
(RXTSEL= 0)
xr
Figure 15
T1/E1/J1
M
E1
E1
E1
E1
E1
E1
E1
E1
T1
T1
T1
T1
J1
J1
J1
J1
ODE
is a

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