XRT83L34ES Exar, XRT83L34ES Datasheet - Page 66
XRT83L34ES
Manufacturer Part Number
XRT83L34ES
Description
Peripheral Drivers & Components - PCIs
Manufacturer
Exar
Datasheet
1.XRT83L34ES.pdf
(99 pages)
Specifications of XRT83L34ES
Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
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XRT83L34
REV. 1.0.1
MICROPROCESSOR REGISTER DESCRIPTIONS
R
EGISTER
0000000
0010000
0100000
0110000
B
D7
D6
D5
D4
D3
D2
D1
D0
IT
A
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
#
DDRESS
C
C
C
C
C
Reserved
Reserved
RXON_n
HANNEL
EQC4_n
EQC3_n
EQC2_n
EQC1_n
EQC0_n
HANNEL
HANNEL
HANNEL
HANNEL
N
AME
T
ABLE
_n
_0
_1
_2
_3
20: M
Receiver ON: Writing a “1” into this bit location turns on the
Receive Section of channel n. Writing a “0” shuts off the
Receiver Section of channel n.
N
Equalizer Control bit 4: This bit together with EQC[3:0] are
used for controlling transmit pulse shaping, transmit line build-
out (LBO) and receive monitoring for either T1 or E1 Modes of
operation.
See
Equalizer Control bit 3: See bit D4 description for function of
this bit
Equalizer Control bit 2: See bit D4 description for function of
this bit
Equalizer Control bit 1: See bit D4 description for function of
this bit
Equalizer Control bit 0: See bit D4 description for function of
this bit
OTES
Table 5
1. This bit provides independent turn-off or turn-on
2. In Hardware mode all receiver channels are always
ICROPROCESSOR
:
control of each receiver channel.
on.
for description of Equalizer Control bits.
63
R
EGISTER
F
UNCTION
#0, B
IT
D
ESCRIPTION
R
EGISTER
xr
T
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
YPE
R
V
ALUE
ESET
0
0
0
0
0
0
0
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