XRT83SL30ES Exar, XRT83SL30ES Datasheet

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... FAX (510) 668-7017 XRT83SL30 REV. 1.0.1 ) ODE MCLKOUT DRIVE DMO MONITOR TTIP TX FILTER LINE & PULSE DRIVER SHAPER TRING LBO[3:0] TXON LOCAL ANALOG LOOPBACK PEAK RTIP RX DETECTOR EQUALIZER RRING & SLICER AISD TEST ICT SDO SCLK SDI RESET • www.exar.com ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGURE LOCK IAGRAM OF THE MCLKE1 MCLKT1 MASTER CLOCK SYNTHESIZER CLKSEL[2:0] TXTEST[0:2] INSBPV QRSS TPOS / TDATA HDB3/ PATTERN TNEG / CODES B8ZS GENERATOR ENCODER ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR • Receiver Line Attenuation Indication Output in 1dB steps • Network Loop-Code Detection for automatic Loop-Back Activation/Deactivation • Transmit All Ones (TAOS) and In-Band Network Loop Up and ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR XRT83SL30 IGURE THE 49 GAUGE 50 RXMUTE 51 RXRES1 52 RXRES0 53 RCLKE 54 TXTEST2 55 TXTEST1 56 TXTEST0 57 TCLKE 58 ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR GENERAL DESCRIPTION .................................................................................................. 1 A .............................................................................................................................................. 1 PPLICATIONS F ................................................................................................................................................... 1 EATURES Figure 1. Block Diagram of the XRT83SL30 T1/E1/J1 LIU (Host Mode) .............................................. 1 Figure 2. Block ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR ABLE ECEIVE ERMINATION Figure 11. Simplified Diagram for the Internal Receive and Transmit Termination Mode ............... ABLE ECEIVE ERMINATIONS Figure ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 32 ABLE ICROPROCESSOR T 33 ABLE ICROPROCESSOR T 34 ABLE ICROPROCESSOR T 35 ABLE ICROPROCESSOR T 36 ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PIN DESCRIPTIONS BY FUNCTION SERIAL INTERFACE IGNAL AME IN YPE HW/HOST 20 SDI 21 EQC4 SDO 22 O EQC3 SCLK 23 EQC2 CS 24 ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR RECEIVER IGNAL AME IN YPE RLOS 63 O RCLK 64 O RNEG 1 O LCV RPOS 2 O RDATA RTIP 4 RRING 5 ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TRANSMITTER IGNAL AME IN YPE TTIP 8 O TRING 10 O TPOS 61 TDATA TNEG 62 CODES TCLK 60 TCLKE 57 TXON 58 D ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TRANSMITTER IGNAL AME IN YPE TXTEST2 54 TXTEST1 55 TXTEST0 Transmit Test Pattern pin 2 Transmit Test Pattern pin 1 ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR JITTER ATTENUATOR IGNAL AME IN YPE JABW 46 JASEL1 47 JASEL0 48 CLOCK SYNTHESIZER IGNAL AME IN YPE MCLKE1 ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR CLOCK SYNTHESIZER IGNAL AME IN YPE MCLKT1 14 MCLKOUT 16 O CLKSEL2 17 CLKSEL1 18 CLKSEL0 Master Clock Input ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REDUNDANCY SUPPORT IGNAL AME IN YPE DMO 11 O TERMINATIONS IGNAL AME IN YPE GAUGE 49 I Twisted Pair ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TERMINATIONS IGNAL AME IN YPE TERSEL1 43 I Termination Impedance Select pin 1 TERSEL0 42 Termination Impedance Select pin 0 In the Hardware ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR CONTROL FUNCTION RESET 41 SR/DR 28 LOOP1 29 LOOP0 30 EQC4 21 SDI EQC3 22 SDO O EQC2 23 SCLK I Hardware Reset (Active "Low") When this pin is ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR CONTROL FUNCTION EQC1 24 CS EQC0 25 INT O ALARM FUNCTION/OTHER IGNAL AME IN YPE ATAOS 27 ICT 59 I Equalizer Control Input ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR ALARM FUNCTION/OTHER IGNAL AME IN YPE NLCDE1 33 NLCDE0 34 INSBPV Network Loop Code Detection Enable pin 1 Network Loop Code ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR ALARM FUNCTION/OTHER IGNAL AME IN YPE NLCD 38 O AISD 39 O QRPD 40 O POWER AND GROUND ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR FUNCTIONAL DESCRIPTION The XRT83SL30 is a fully integrated single channel short-haul transceiver intended for T1 systems. Simplified block diagrams of the device are shown in In ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR MCLKE1 MCLKT1 CLKSEL2 2048 2048 2048 2048 2048 1544 1544 1544 1544 1544 2048 1544 ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR RECEIVE MONITOR MODE In applications where Monitor mode is desired, the equalizer can be configured in a gain mode which handles input signals attenuated resistively up to 29dB, along ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+29dB), the receiver will declare RLOS if the signal is attenuated by an ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR JITTER ATTENUATOR To reduce phase and frequency jitter in the recovered clock, the jitter attenuator can be placed in the receive signal path. The jitter attenuator uses a data ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR ARBITRARY PULSE GENERATOR In T1 mode only, the arbitrary pulse generator divides the pulse into eight individual segments. Each segment is set by a 7-Bit binary word by ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR F 10 IGURE RANSMIT LOCK AND TCLK TPOS/TDATA or TNEG T SU TRANSMIT HDB3/B8ZS ENCODER The Encoder function is available in both Hardware and Host modes ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and TRING. Driver failure may be caused by a short circuit ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TRANSMIT AND RECEIVE TERMINATIONS The XRT83SL30 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide applications for T1, J1 and E1. ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR RXTSEL TERSEL1 TERSEL0 ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR F 13. S IGURE IMPLIFIED XRT83SL30 LIU TTIP TRING RTIP RRING TRANSMITTER RANSMIT ERMINATION ODE In Hardware mode, TXTSEL (Pin 45) can be tied “High” to ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T ABLE Table 11 summarizes the transmit terminations. TERSEL1 TERSEL0 100 Ω 110 Ω ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PROGRAMMING CONSIDERATIONS In many applications switching the control of the transmitter outputs and the receiver line impedance to hardware control will provide faster transmitter ON/OFF switching. In Host Mode, ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR F 14 IGURE IMPLIFIED LOCK Backplane Interface Primary Card TxTSEL=1, Internal Backup Card TxTSEL=1, Internal RECEIVE 1:1 & 1+1 REDUNDANCY For 1:1 and 1+1 redundancy, the ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR F 15. S IGURE IMPLIFIED Backplane Interface Primary Card RxTSEL=1, Internal Backup Card RxTSEL=0, External N+1 REDUNDANCY N+1 redundancy has one backup card for N primary cards. Due to ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR F 16 IGURE IMPLIFIED LOCK Backplane Interface Primary Card TxTSEL=1, Internal Primary Card TxTSEL=1, Internal Primary Card TxTSEL=1, Internal Backup Card TxTSEL=1, Internal - T ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR RECEIVE For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance mode. The receivers on the backup card should be programmed for external impedance ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PATTERN TRANSMIT AND DETECT FUNCTION Several test and diagnostic patterns can be generated and detected by the chip. In Hardware mode the channel can be programmed to transmit ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR NLCDE[1:0] control the Loop-Code detection according to T ABLE NLCDE1 NLCDE0 0 0 Disable Loop-Code Detection 0 1 Detect Loop-Up Code in Receive Data 1 0 Detect Loop-Down Code ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR With TDQRSS activated, a bit error can be inserted in the transmitted QRSS pattern by transitioning the INSBER interface bit from “0” to “1”. Bipolar violation can also ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR LOOP-BACK MODES The XRT83SL30 supports several Loop-Back modes under both Hardware and Host control. In Hardware mode the two LOOP[1:0] pins control the Loop-Back functions according to T ABLE ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REMOTE LOOP-BACK (RLOOP) With Remote Loop-Back activated, receive data after the jitter attenuator (if selected in the receive path) is looped back to the transmit path using RCLK ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR DIGITAL LOOP-BACK (DLOOP) Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the corresponding receiver output pins through the encoder/decoder and jitter ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR HOST MODE SERIAL INTERFACE OPERATION XRT83SL30 has a simple four wire Serial Interface that is compatible with many of the microcontrollers available in the market. The Host mode ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR Bit 2 through 6:The five (5) Address Values (labeled A0, A1, A2, A3 and A4) The next five rising edges of the SCLK signal, clock in the 5-bit address ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T ABLE R EGISTER R N EGISTER UMBER HEX 0x00 - 0x12 0x13 - 0x15 0x16 - 0x1D 30 ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T ABLE DDRESS IT T YPE 15 01111 R/W X Hex 0x0F 16 10000 R/W SR/DR Hex 0x10 17 ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 18: M ABLE R A EGISTER DDRESS 00000 AME D7 Reserved D6 Reserved D5 Reserved D4 EQC4 Equalizer Control bit 4: This bit ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 19: M ABLE R A EGISTER DDRESS 00001 AME D7 RXTSEL Receiver Termination Select: In Host mode, this bit is used to select between ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 19: M ABLE D3 JASEL1 Jitter Attenuator select bit 1: The JASEL1 and JASEL0 bits are used to disable or place the jitter attenuator in the transmit ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 20: M ABLE R A EGISTER DDRESS 00010 AME D7 RXON Receiver ON: Writing a “1” into this bit location turns on the Receive ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 20: M ABLE D3 TXON Transmitter ON: Writing a "1" into this bit location turns on the Transmit Section. A ‘0’ in this bit location, shuts off ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 21: M ABLE R A EGISTER DDRESS 00011 AME D7 NLCDE1 Network Loop Code Detection Enable bit 1: This bit together with NLCDE0, Control ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 21: M ABLE D4 RXRES1 Receive External Resistor Control pin 1: In Host mode, this bit along with the RXRES0 bit selects the value of the external ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 22: M ABLE R A EGISTER DDRESS 00100 AME D7 GIE Global Interrupt Enable: Writing a "1" into this bit, globally enables interrupt generation ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 23: M ABLE R A EGISTER DDRESS 00101 AME D7 Reserved D6 DMO Driver Monitor Output: This bit is set to a "1" ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 23: M ABLE D3 NLCD Network Loop-Code Detection: This bit operates differently in the Manual or the Automatic Net- work Loop-Code detection modes. In the Manual Loop-Code detection ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 24: M ABLE R A EGISTER DDRESS 00110 AME D7 Reserved D6 DMOIS Driver Monitor Output Interrupt Status: This bit is set to ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 25: M ABLE R A EGISTER DDRESS 00111 AME D7 Reserved D6 Reserved D5 CLOS5 Cable Loss bit 5: CLOS[5:0] are the six bits ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 27: M ABLE R A EGISTER DDRESS 01001 AME D7 Reserved D6-D0 B6S2 - B0S2 Arbitrary Transmit Pulse Shape, Segment 2 The shape ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 29: M ABLE R A EGISTER DDRESS 01011 AME D7 Reserved D6-D0 B6S4 - B0S4 Arbitrary Transmit Pulse Shape, Segment 4 The shape of ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 31: M ABLE R A EGISTER DDRESS 01101 AME D7 Reserved D6-D0 B6S6 - B0S6 Arbitrary Transmit Pulse Shape, Segment 6 The shape ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 33: M ABLE R A EGISTER DDRESS 01111 AME D7 Reserved D6-D0 B6S8 - B0S8 Arbitrary Transmit Pulse Shape, Segment 8 The shape of ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 34: M ABLE R A EGISTER DDRESS 10000 N AME SR/DR Single-rail/Dual-rail Select: Writing a "1" to this bit configures the XRT83SL30 to ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 35: M ABLE R A EGISTER DDRESS 10001 N AME Reserved D6 CLKSEL2 Clock Select Inputs for Master Clock Synthesizer bit ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 35: M ABLE D3 MCLKRATE Master Clock Rate Select: The state of this bit programs the Master Clock Synthesizer to generate the T1/ clock. The ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 36: M ABLE D3 SL_1 Slicer Level Control bit 1: This bit and bit D2 control the slic- ing level for the slicer per the following table. D2 ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR ELECTRICAL CHARACTERISTICS Storage Temperature...............-65°C to +150°C Operating Temperature............. -40°C to +85°C Supply Voltage............................-0.5V to +3.8V Vin................................................-0.5 to +5. ABLE VDD=3.3V±5 ARAMETER Power ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 40 ABLE VDD=3.3V±5 ARAMETER Receiver loss of signal: Number of consecutive zeros before RLOS is set Input signal level at RLOS RLOS De-asserted Receiver ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 41 ABLE VDD=3.3V±5 ARAMETER Input Impedance Jitter Tolerance: 1Hz 10kHz - 100kHz Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude Jitter Attenuator Corner ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 44 ABLE VDD=3.3V±5 ARAMETER AMI Output Pulse Amplitude: Output Pulse Width Output Pulse Width Imbalance Output Pulse Amplitude Imbalance Jitter Added by the Transmitter ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T ABLE Test Load Impedance Nominal Peak Voltage of a Mark Peak voltage of a Space (no Mark) Nominal Pulse width Ratio of Positive and Negative Pulses Imbalance ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 46: DSX1 I ABLE M INIMUM CURVE T (UI) N IME ORMALIZED AMPLITUDE 0.66 0.93 -0.05V 1.16 -0.05V T ABLE (T =25°C, VDD=3.3V±5 ARAMETER E1 MCLK ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR F 26 IGURE RANSMIT LOCK AND TCLK TPOS/TDATA or TNEG 27 IGURE ECEIVE LOCK AND UTPUT R DY RCLK ...

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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PACKAGE DIMENSIONS A Seating Plane Note: The control dimension is the millimeter column SYMBOL α 64 LEAD ...

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REV. 1.0.1 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR ORDERING INFORMATION P # ART XRT83SL30IV T I HERMAL NFORMATION REVISION HISTORY Rev. P1.0.0 Initial issue. Rev. P1.0.1 Removed TERCNTL function (pin 46). Pins 61 and 62 are ...

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... XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...