XRT83SL30ES Exar, XRT83SL30ES Datasheet - Page 12

• Manufacturer Part Number: XRT83SL30ES
• Description: Peripheral Drivers & Components - PCIs 1 CHT1/E1 LIUSH
• Manufacturer: Exar

Specifications of XRT83SL30ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

JITTER ATTENUATOR
CLOCK SYNTHESIZER
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
S
S
IGNAL
IGNAL
MCLKE1
JASEL1
JASEL0
JABW
N
N
AME
AME
P
P
46
47
48
13
IN
IN
#
#
T
T
YPE
YPE
I
I
I
Jitter Attenuator Bandwidth
In Hardware and E1 mode, when JABW=”0” the jitter attenuator bandwidth
is 10Hz (normal mode). Setting JABW to “1” selects a 1.5Hz Bandwidth for
the Jitter Attenuator and the FIFO length will be automatically set to 64 bits.
In T1 mode the Jitter Attenuator Bandwidth is always set to 3Hz, and the
state of this pin has no effect on the Bandwidth. See table under JASEL[1:0]
pin, below.
N
Jitter Attenuator select pin 1
Jitter Attenuator select pin 0
In Hardware Mode, JASEL0, JASEL1 and JABW pins are used to place the
jitter attenuator in the transmit path, the receive path or to disable it and set
the jitter attenuator bandwidth and FIFO size per the following table.
N
E1 Master Clock Input
This input signal is an independent 2.048MHz clock for E1 system with
required accuracy of better than ±50ppm and a duty cycle of 40% to 60%.
MCLKE1 is used in the E1 mode. Its function is to provide internal timing for
the PLL clock recovery circuit, transmit pulse shaping, jitter attenuator block,
reference clock during transmit all ones data and timing reference for the
microprocessor in Host Mode operation.
MCLKE1 is also input to a programmable frequency synthesizer that under
the control of the CLKSEL[2:0] inputs can be used to generate a master
clock from an accurate external source. In systems that have only one mas-
ter clock source available (E1 or T1), that clock should be connected to both
MCLKE1 and MCLKT1 inputs for proper operation.
N
OTE
OTE
OTES
JABW
1. See pin descriptions for pins CLKSEL[2:0].
2. Internally pulled “Low” with a 50kΩ resistor.
: Internally pulled “Low” with a 50kΩ resistor.
: These pins are internally pulled "Low" with 50kΩ resistors.
0
0
0
0
1
1
1
1
:
JASEL1
9
0
0
1
1
0
0
1
1
JASEL0
0
1
0
1
0
1
0
1
D
D
ESCRIPTION
ESCRIPTION
Disabled
Transmit
Disabled
Transmit
JA Path
Receive
Receive
Receive
Receive
------
------
JA BW (Hz)
T1
3
3
3
3
3
3
------
------
1.5
1.5
1.5
E1
10
10
10
FIFO Size
T1/E1
--------
32/32
32/32
64/64
32/64
32/64
64/64
------
REV. 1.0.1