XRT83SL30ES Exar, XRT83SL30ES Datasheet - Page 54

• Manufacturer Part Number: XRT83SL30ES
• Description: Peripheral Drivers & Components - PCIs 1 CHT1/E1 LIUSH
• Manufacturer: Exar

Specifications of XRT83SL30ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
R
EGISTER
00100
B
D7
D6
D5
D4
D3
D2
D1
D0
IT
A
#
DDRESS
QRPDIE
NLCDIE
RLOSIE
DMOIE
AISDIE
LCVIE
FLSIE
N
GIE
AME
T
ABLE
22: M
Global Interrupt Enable: Writing a "1" into this bit, globally
enables interrupt generation on the INT pin. Writing a "0" into this
bit, globally masks all interrupt requests.
DMO Interrupt Enable: Writing a "1" to this bit enables DMO
interrupt generation, writing a "0" masks it.
FIFO Limit Status Interrupt Enable: Writing a "1" to this bit
enables interrupt generation when the FIFO limit is within 3 bits,
writing a "0" to masks it.
Line Code Violation Interrupt Enable: Writing a "1" to this bit
enables Line Code Violation interrupt generation, writing a "0"
masks it.
Network Loop-Code Detection Interrupt Enable: Writing a "1"
to this bit enables Network Loop-code detection interrupt genera-
tion, writing a "0" masks it.
AIS Detection Interrupt Enable: Writing a "1" to this bit enables
Alarm Indication Signal detection interrupt generation, writing a
"0" masks it.
Receive Loss of Signal Interrupt Enable: Writing a "1" to this
bit enables Loss of Receive Signal interrupt generation, writing a
"0" masks it.
QRSS Pattern Detection Interrupt Enable: Writing a "1" to this
bit enables QRSS pattern detection interrupt generation, writing
a "0" masks it.
ICROPROCESSOR
51
R
EGISTER
F
UNCTION
#4
BIT DESCRIPTION
R
EGISTER
T
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
YPE
REV. 1.0.1
R
V
ALUE
ESET
0
0
0
0
0
0
0
0