XRT83SL30ES Exar, XRT83SL30ES Datasheet - Page 6

• Manufacturer Part Number: XRT83SL30ES
• Description: Peripheral Drivers & Components - PCIs 1 CHT1/E1 LIUSH
• Manufacturer: Exar

Specifications of XRT83SL30ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
HOST MODE SERIAL INTERFACE OPERATION .......................................................... 40
T
Figure 11. Simplified Diagram for the Internal Receive and Transmit Termination Mode ............... 25
T
Figure 12. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) .................... 26
Figure 13. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) .......................... 27
TRANSMITTER ........................................................................................................................................ 27
T
T
T
T
REDUNDANCY APPLICATIONS ............................................................................................................. 28
TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 29
Figure 14. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy .............. 30
Figure 15. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy .................... 31
Figure 16. Simplified Block Diagram - Transmit Section for N+1 Redundancy ................................ 32
Figure 17. Simplified Block Diagram - Receive Section for N+1 Redundancy ................................. 33
P
T
T
N
T
T
L
T
T
L
Figure 18. Local Analog Loop-back signal flow .................................................................................. 37
R
Figure 19. Remote Loop-back mode with jitter attenuator selected in receive path ....................... 38
Figure 20. Remote Loop-back mode with jitter attenuator selected in Transmit path ..................... 38
D
Figure 21. Digital Loop-back mode with jitter attenuator selected in Transmit path ....................... 39
D
Figure 22. Signal flow in Dual loop-back mode ................................................................................... 39
U
Figure 23. Microprocessor Serial Interface Data Structure ................................................................ 41
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OOP
OCAL
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
RANSMIT
ABLE
RANSMIT AND
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ATTERN
ETWORK
EMOTE
IGITAL
UAL
SING THE
Transmit Termination Mode .............................................................................................................................. 27
External Transmit Termination Mode ............................................................................................................... 27
-B
L
A
6: R
7: R
8: T
9: T
10: T
11: T
12: P
13: L
14: L
15: L
OOP
16: M
17: M
18: M
19: M
20: M
21: M
22: M
23: M
24: M
25: M
26: M
27: M
28: M
29: M
30: M
31: M
ACK
L
NALOG
L
OOP
T
OOP
A
L
RANSMIT AND
RANSMIT
ERMINATION
M
-B
ECEIVE
ECEIVE
OOP
LL
M
RANSMIT
RANSMIT
OOP
OOP
OOP
ATTERN TRANSMISSION CONTROL
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
-B
ACK
ODES
-B
O
D
L
ACK
NES
C
-C
ETECT
-
-
ACK
OOP
BACK CONTROL IN
BACK CONTROL IN
ODE
...................................................................................................................................... 39
T
T
ODE
.................................................................................................................................... 37
ERMINATION
ERMINATIONS
T
(DLOOP) ................................................................................................................... 39
(TAOS) ..................................................................................................................... 34
-B
(RLOOP) .................................................................................................................. 38
ERMINATION
T
T
D
ERMINATION
ERMINATIONS
Q
ACK
S
D
D
ETECTION AND
ELECT
UASI
ETECTION
ETECT
(ALOOP) ........................................................................................................ 37
-R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
S
C
ERIAL
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
ANDOM
C
F
ONTROL
.............................................................................................................. 26
C
ONTROL
UNCTION
C
C
H
H
ONTROL
.......................................................................................................... 28
ONTROL
ONTROL
ARDWARE MODE
OST MODE
I
NTERFACE
T
S
RANSMISSION
A
B
#0
#1
#2
#3
#4
#5
#6
#7
#8
#9
#10
#11
#12
#13
IGNAL
DDRESS
IT
................................................................................................. 27
................................................................................................ 25
............................................................................................... 34
BIT DESCRIPTION
BIT DESCRIPTION
BIT DESCRIPTION
BIT DESCRIPTION
BIT DESCRIPTION
BIT DESCRIPTION
BIT DESCRIPTION
BIT DESCRIPTION
BIT DESCRIPTION
BIT DESCRIPTION
.............................................................................................. 27
M
BIT DESCRIPTION
BIT DESCRIPTION
BIT DESCRIPTION
BIT DESCRIPTION
............................................................................................ 28
............................................................................................ 34
............................................................................................ 35
AP
S
........................................................................................ 37
OURCE
...................................................................................... 40
..................................................................................... 42
.................................................................................... 42
II
............................................................................... 34
............................................................................... 37
(TDQRSS) ......................................................... 35
.................................................................... 44
.................................................................... 45
.................................................................... 47
.................................................................... 49
.................................................................... 51
.................................................................... 52
.................................................................... 54
.................................................................... 55
.................................................................... 55
.................................................................... 56
.................................................................. 56
.................................................................. 57
.................................................................. 57
.................................................................. 58
REV. 1.0.1