P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet - Page 114

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P5010NXN1QMB

Manufacturer Part Number
P5010NXN1QMB
Description
Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of P5010NXN1QMB

Rohs
yes
DC input impedance
Powered down DC input
impedance
Electrical idle detect threshold
Note:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there
3. The Rx DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure
Electrical Characteristics
Table 66. PCI Express 2.0 (5 GT/s) Differential Receiver (Rx) Input DC Specifications (SV
114
is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at
300 mV above the Rx ground.
Parameter
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
V
RX-IDLE-DET-DIFFp-p
Z
RX-HIGH-IMP-DC
Symbol
Z
RX-DC
Min
40
50
65
(continued)
Typ
50
Max
175
60
Unit
mV V
Ω
Required Rx D+ as well as D– DC
Impedance (50 ±20% tolerance).
See Notes 1 and 2.
Required Rx D+ as well as D– DC
Impedance when the Receiver
terminations do not have power.
See Note 3.
2 × |V
Measured at the package pins of the
receiver
RX-IDLE-DET-DIFFp-p
RX-D+
Freescale Semiconductor
– V
DD
RX-D–
= 1.5 V or 1.8 V)
Note
=
|

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