P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet - Page 147

• Manufacturer Part Number: P5010NXN1QMB
• Description: Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXN1QMB

• Rohs: yes

have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected
to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON).
3.5
The SerDes block requires a clean, tightly regulated source of power (SV
reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.
Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to power and ground must be
done with multiple vias to further reduce inductance.
3.6
To ensure reliable chip operation, it is highly recommended that the user note the following:
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First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible to the supply balls
of the device. Where the board has blind vias, these capacitors must be placed directly below the chip supply and
ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the
device as close to the supply and ground connections as possible.
Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be done for all SerDes
supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-µF, low ESR SMT tantalum chip
capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies.
Connect unused inputs to an appropriate signal level. All unused active low inputs should be tied to V
CV
(no-connect) signals must remain unconnected. Power and ground connections should be made to all external V
BV
The Ethernet controllers 1 and/or 2 input pins may be disabled by setting their respective RCW Configuration field
EC1 (bits 360–361), and EC2 (bits 363–364), to 0b11 = No parallel mode Ethernet. When disabled, these inputs do
not need to be externally pulled to an appropriate signal level.
ECn_GTX_CLK125 is a 125-MHz input clock on the dTSEC ports. If the dTSEC ports are not used for RGMII, the
ECn_GTX_CLK125 input can be tied off to GND.
If RCW field DMA1=0b1 (RCW bit 384), the DMA1 external interface is not enabled and this pin should be left as a
no connect.
If RCW field I2C = 0b100 or 0b101 (RCW bits 355–357), the SDHC_WP and SDHC_CD input signals are enabled
for external use. If SDHC_WP and SDHC_CD are selected and not used, they must be externally pulled low such that
SDHC_WP = 0 (write enabled) and SDHC_CD = 0 (card detected). If RCW field I2C != 0b100 or 0b101, thereby
selecting either I2C3 or GPIO functionality, SDHC_WP and SDHC_CD are internally driven such that SDHC_WP =
write enabled and SDHC_CD = card detected and the selected I2C3 or GPIO external pin functionality may be used.
For P5010 without security (SVR = 0x8221_0010) or P5010E (SVR = 0x8229_0010), TEST_SEL must be connected
to GND.
The TMP_DETECT pin is an active low input to the Security Monitor (see Chapter “Secure Boot and Trust
Architecture” in the reference manual for your chip). When using Trust Architecture functionality, external logic must
ramp TMP_DETECT with OV
to prevent the input from going low.
TMP_DETECT pin and LP_TMP DETECT pin are active low input to the Security Monitor (see the “Secure Boot and
Trust Architecture” chapter of the applicable chip reference manual). If a tamper sensor is used, it must maintain the
signal at the specified voltage until a tamper is detected. 1K pull-down resistor strongly recommended. If Trust is used
without tamper sensors, tie high.VDD_LP must be connected even if Low Power features are not used. Otherwise the
LP_Section will generate internal errors, which will prevent the high power trust section from reaching Trusted/Secure
state.
SerDes Block Power Supply Decoupling Recommendations
Connection Recommendations
DD
DD
, OV
, CV
DD
DD
, OV
, GV
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
DD
DD
, GV
, and LV
DD
, LV
DD
DD
. If not using Trust Architecture functionality, TMP_DETECT must be tied to OV
DD,
as required. All unused active high inputs should be connected to GND. All NC
and GND pins of the device.
DD
and XV
DD
) to ensure low jitter on transmit and
Hardware Design Considerations
DD,
BV
DD
DD
,
147
DD
,