P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet - Page 129

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P5010NXN1QMB

Manufacturer Part Number
P5010NXN1QMB
Description
Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of P5010NXN1QMB

Rohs
yes
2.20.8.2.1
The AC requirements for the SATA reference clock are listed in this table to be guaranteed by the customer’s application design.
This figure shows the reference clock timing waveform.
Freescale Semiconductor
For recommended operating conditions, see
SD_REF_CLK/SD_REF_CLK frequency range
SD_REF_CLK/SD_REF_CLK clock frequency tolerance
SD_REF_CLK/SD_REF_CLK reference clock duty cycle
(measured at 1.6 V)
SD_REF_CLK/SD_REF_CLK cycle-to-cycle clock jitter
(period jitter)
SD_REF_CLK/SD_REF_CLK total reference clock jitter,
phase jitter (peak-peak)
Note:
1. Caution: Only 100, and 125 MHz have been tested. In-between values do not work correctly with the rest of the system.
2. At RefClk input
3. In a frequency band from 150 kHz to 15 MHz at BER of 10
4. Total peak-to-peak deterministic jitter should be less than or equal to 50 ps.
AC Requirements for SATA REF_CLK
Ref_CLK
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Parameter
Table 88. SATA Reference Clock Input Requirements
Figure 47. Reference Clock Timing Waveform
Table
3.
T
L
-12
t
t
CLK_DUTY
t
Symbol
CLK_REF
CLK_TOL
t
t
CLK_CJ
CLK_PJ
T
H
–350
Min
–50
40
100/125
Typ
50
Electrical Characteristics
+350
Max
100
+50
60
Unit
MHz
ppm
ps
ps
%
2, 3,
Note
1
2
129
4

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