P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet - Page 122

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P5010NXN1QMB

Manufacturer Part Number
P5010NXN1QMB
Description
Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of P5010NXN1QMB

Rohs
yes
Electrical Characteristics
This figure shows the single-frequency sinusoidal jitter limits.
2.20.6
This section describes the DC and AC electrical specifications for the XAUI bus.
2.20.6.1
This section discusses the XAUI DC electrical characteristics for the clocking signals, transmitter, and receiver.
122
For recommended operating conditions, see
Unit Interval: 2.5 GBaud
Unit Interval: 3.125 GBaud
Unit Interval: 5.0 GBaud
Note:
1. Measured at receiver.
2. Total jitter is composed of three components: deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of
is included to ensure margin for low-frequency jitter, wander, noise, crosstalk, and other variable system effects.
8.5 UI p-p
0.10 UI p-p
Sinusoidal
Amplitude
Jitter
XAUI
Parameter
XAUI DC Electrical Characteristics
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Table 74. sRIO Receiver AC Timing Specifications (continued)
22.1 kHz
Figure 46. Single-Frequency Sinusoidal Jitter Limits
Table
3.
Symbol
UI
UI
UI
Frequency
400 – 100ppm
320 – 100ppm
200 – 100ppm
Min
Typical
400
320
200
1.875 MHz
Figure
400 + 100ppm
320 + 100ppm
200 + 100ppm
46. The sinusoidal jitter component
Max
20 MHz
Freescale Semiconductor
Unit
ps
ps
ps
Note

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