P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet - Page 60

• Manufacturer Part Number: P5010NXN1QMB
• Description: Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXN1QMB

• Rohs: yes

Electrical Characteristics
2.1.3
This table provides information about the characteristics of the output driver strengths. The values are preliminary estimates.
2.2
The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation. These
requirements are as follows for power up:
60
Local Bus interface utilities signals
DDR3 signal
DDR3L signal
eTSEC/10/100 signals
DUART, system control, JTAG
I
eSPI and SD/MMC
Note:
2
1. The drive strength of the DDR3 or DDR3L interface in half-strength mode is at T
C
2.
3.
4.
5.
6.
Bring up OV
— PORESET input must be driven asserted and held during this step
— IO_VSEL inputs must be driven during this step and held stable during normal operation.
— USB_V
Bring up V
USB_V
Bring up GV
Negate PORESET input as long as the required assertion/hold time has been met per
For secure boot fuse programming: After negation of PORESET, drive POV
delay per
power cycled (PORESET assertion) or powered down (V
Table
Power Up Sequencing
Output Driver Characteristics
5. See
DD
Only two secure boot fuse programming events are permitted per lifetime of a device.
No activity other than that required for secure boot fuse programming is permitted while
POV
reading of the fuse block may only occur while POV
Table
_1P0 must be ramped up simultaneously.
DD_PL
DD
Section 5, “Security Fuse Processor,”
DD
DD
DD
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Driver Type
_3P3 rise time (10% to 90%) has a minimum of 350 μs.
, LV
5. After fuse programming is completed, it is required to return POV
and XV
, V
driven to any voltage above GND, including the reading of the fuse block. The
DD_CA
DD
, BV
DD
, V
.
DD
DD_CB
, CV
Table 4. Output Drive Capability
DD
, SV
, and USB_V
DD
, AV
WARNING
DD
for additional details.
(cores, platform, DDR, SerDes) and USB_V
DD
Output Impedance (Ω)
40 (half-strength mode)
40 (half-strength mode)
20 (full-strength mode)
20 (full-strength mode)
_3P3. Drive POV
DD_PL
DD
45
45
45
45
45
45
45
45
45
45
ramp down) per the required timing specified in
= GND.
DD
j
= 105 °C and at GV
= GND.
DD
= 1.5 V after a required minimum
(Nominal) Supply
GV
GV
OV
OV
CV
CV
CV
BV
BV
BV
LV
LV
DD
Table
DD
Voltage
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
= GND before the system is
= 1.35 V
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
= 1.8 V
= 3.3 V
= 3.3 V
= 3.3 V
= 2.5 V
= 1.8 V
= 1.5 V
17.
Freescale Semiconductor
DD
DD
_1P0. V
(min).
DD_PL
Note
—
—
—
—
—
1
1
and