P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet - Page 120

• Manufacturer Part Number: P5010NXN1QMB
• Description: Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXN1QMB

• Rohs: yes

Electrical Characteristics
2.20.5.2
With the use of high-speed serial links, the interconnect media causes degradation of the signal at the receiver and produces
effects such as inter-symbol interference (ISI) or data-dependent jitter. This loss can be large enough to degrade the eye opening
at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be used. The
most common equalization techniques that can be used are as follows:
2.20.5.3
SerDes bank 1 and bank 3 (SD_REF_CLK1 and SD_REF_CLK1) may be used for various SerDes serial RapidIO
configurations based on the RCW Configuration field SRDS_PRTCL. The serial RapidIO interface is not supported on SerDes
banks 2.
For more information on these specifications, see
2.20.5.4
This section explains the DC requirements for the serial RapidIO interface.
2.20.5.4.1
LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section.
The differential return loss, S11, of the transmitter in each case is better than the following:
The reference impedance for the differential return loss measurements is 100-Ω resistive. Differential return loss includes
contributions from on-chip circuitry, chip packaging, and any off-chip components related to the driver. The output impedance
requirement applies to all valid output levels.
It is recommended that the 20%–80% rise/fall time of the transmitter, as measured at the transmitter output, have a minimum
value 60 ps in each case.
It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals that comprise a
differential pair not exceed 20 ps at 2.50 GBaud and 15 ps at 3.125 GBaud.
This table defines the transmitter DC specifications for the serial RapidIO interface operating at XV
120
For recommended operating conditions, see
Output Voltage,
Long-run differential output voltage
Short-run differential output voltage
Note:
1. Voltage relative to COMMON of either signal comprising a differential pair.
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•
•
•
•
Pre-emphasis on the transmitter
A passive high-pass filter network placed at the receiver, often referred to as passive equalization.
The use of active circuits in the receiver, often referred to as adaptive equalization.
–10 dB for (Baud Frequency) ÷ 10 < Freq(f) < 625 MHz
–10 dB + 10log(f ÷ 625 MHz) dB for 625 MHz ≤ Freq(f) ≤ Baud Frequency
Table 71. sRIO Transmitter DC Timing Specifications—2.5 GBaud, 3.125 GBaud, 5 GBaud
Equalization
Serial RapidIO Clocking Requirements for SD_REF_CLKn and
SD_REF_CLKn
DC Requirements for Serial RapidIO
Parameter
DC Serial RapidIO Timing Transmitter Specifications
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Table
3.
Symbol
V
V
DIFFPP
DIFFPP
Section 2.20.2, “SerDes Reference Clocks.”
V
O
–0.40
Min
800
500
Typ
—
—
—
1600
1000
Max
2.30
DD
Freescale Semiconductor
mV p-p
mV p-p
= 1.5 V or 1.8 V.
Unit
V
Note
—
—
1