P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet - Page 138

• Manufacturer Part Number: P5010NXN1QMB
• Description: Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXN1QMB

• Rohs: yes

Hardware Design Considerations
3.1.2
The allowed platform clock to SYSCLK ratios are shown in this table.
Note that in synchronous DDR mode, the DDR data rate is the determining factor for selecting the platform bus frequency
because the platform frequency must equal the DDR data rate.
In asynchronous DDR mode, the memory bus clock frequency is decoupled from the platform bus frequency.
3.1.3
The clock ratio between SYSCLK and each of the two core complex PLLs is determined at power up by the binary value of the
RCW field CCn_PLL_RAT. This table describes the supported ratios. Note that a core complex PLL frequency targeting 1 GHz
and above must set RCW field CCn_PLL_CFG = 0b00, for frequency targeting below 1 GHz set CCn_PLL_CFG = 0b01.
This table lists the supported Core Complex to SYSCLK ratios.
138
Platform to SYSCLK PLL Ratio
e5500-64 Core Complex to SYSCLK PLL Ratio
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Table 101. e5500 Core Complex PLL to SYSCLK Ratios
Binary Value of CCn_PLL_RAT
Table 100. Platform to SYSCLK PLL Ratios
Binary Value of
SYS_PLL_RAT
All Others
All Others
0_1000
0_1001
0_1010
0_1011
0_1100
0_1110
0_1111
1_0000
1_0001
1_0010
0_0100
0_0101
0_0110
0_0111
0_1000
Platform:SYSCLK Ratio
Core Complex:SYSCLK
Reserved
4:1
5:1
6:1
7:1
8:1
Reserved
Ratio
10:1
11:1
12:1
14:1
15:1
16:1
17:1
18:1
8:1
9:1
Freescale Semiconductor