P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet - Page 88

• Manufacturer Part Number: P5010NXN1QMB
• Description: Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXN1QMB

• Rohs: yes

Electrical Characteristics
This figure shows the Ethernet Management Interface timing diagram.
2.12.4
This table provides the IEEE 1588 AC timing specifications.
88
For recommended operating conditions, see
For recommended operating conditions, see
TSEC_1588_CLK clock period
TSEC_1588_CLK duty cycle
TSEC_1588_CLK peak-to-peak jitter
Rise time eTSEC_1588_CLK (20%–80%)
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
Note:
1. The symbols used for timing specifications follow the pattern of t
2. This parameter is dependent on the frame manager clock frequency (MIIMCFG [MgmtClk] field determines the clock
3. This parameter is dependent on the management data clock frequency, f
inputs and t
management data timing (MD) for the time t
data hold time. Also, t
the valid state (V) relative to the t
frequency of the MgmtClk Clock EC_MDC).
clock period ±6 ns. For example, with a management data clock of 2.5 MHz, the min/max delay is 200 ns ± 6 ns.
Parameter/Condition
eTSEC IEEE Std 1588 AC Specifications
Table 43. Ethernet Management Interface 2 AC Timing Specifications (continued)
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
(Output)
(Input)
MDIO
MDIO
MDC
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
MDDVKH
Figure 20. Ethernet Management Interface Timing Diagram
Table 44. eTSEC IEEE 1588 AC Timing Specifications
symbolizes management data timing (MD) with respect to the time data input signals (D) reach
MDC
t
MDCH
Table
Table 3.
Symbol
t
t
t
MDKHDX
MDDXKH
MDDVKH
clock reference (K) going to the high (H) state or setup time.
t
MDDVKH
3.
t
MDC
t
MDC
t
1
t
T1588CLKINR
T1588CLKINJ
T1588CLKH
t
t
t
MDKHDX
Symbol
T1588CLK
T1588CLK
from clock reference (K) high (H) until data outputs (D) are invalid (X) or
(0.5 ×(1/f
/
Min
8
0
MDC
t
MDCF
)) – 6
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
Min
3.3
1.0
40
—
t
MDDXKH
MDC
Typ
t
—
—
—
MDCR
. The delay is equal to 0.5 management data
Typ
50
—
—
—
(0.5 ×(1/f
Max
T
MDKHDX
—
—
RX_CLK
MDC
Max
250
2.0
60
Freescale Semiconductor
)) + 6
symbolizes
× 7
Unit
Unit
ns
ns
ns
ns
ps
ns
%
Note
Note
1,
—
—
—
—
for
3
3
2