MCIMX6S1AVM08ABR Freescale Semiconductor, MCIMX6S1AVM08ABR Datasheet - Page 104

• Manufacturer Part Number: MCIMX6S1AVM08ABR
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S1AVM08ABR

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 16 KB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: Parallel
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Electrical Characteristics
104
i.MX 6Solo/6DualLite
DISPx_DAT10
DISPx_DAT11
DISPx_DAT12
DISPx_DAT13
DISPx_DAT14
DISPx_DAT15
DISPx_DAT16
DISPx_DAT17
DISPx_DAT18
DISPx_DAT19
DISPx_DAT20
DISPx_DAT21
DISPx_DAT0
DISPx_DAT1
DISPx_DAT2
DISPx_DAT3
DISPx_DAT4
DISPx_DAT5
DISPx_DAT6
DISPx_DAT7
DISPx_DAT8
DISPx_DAT9
Port Name
(x=0, 1)
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
(General)
DAT[10]
DAT[11]
DAT[12]
DAT[13]
DAT[14]
DAT[15]
DAT[16]
DAT[17]
DAT[18]
DAT[19]
DAT[20]
DAT[21]
Signal
DAT[0]
DAT[1]
DAT[2]
DAT[3]
DAT[4]
DAT[5]
DAT[6]
DAT[7]
DAT[8]
DAT[9]
Name
RGB,
16-bit
Table 71. Video Signal Cross-Reference
RGB
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
R[0]
R[1]
R[2]
R[3]
R[4]
B[0]
B[1]
B[2]
B[3]
B[4]
—
—
—
—
—
—
RGB/TV Signal Allocation (Example)
18-bit
RGB
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
—
—
—
—
24 Bit
RGB
LCD
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
YCrCb
Y/C[0]
Y/C[1]
Y/C[2]
Y/C[3]
Y/C[4]
Y/C[5]
Y/C[6]
Y/C[7]
8-bit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
YCrCb
16-bit
C[0]
C[1]
C[2]
C[3]
C[4]
C[5]
C[6]
C[7]
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
—
—
—
—
—
—
YCrCb
20-bit
C[0]
C[1]
C[2]
C[3]
C[4]
C[5]
C[6]
C[7]
C[8]
C[9]
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
Y[8]
Y[9]
—
—
The restrictions are as follows:
• There are maximal three
• The bit order is expressed in
continuous groups of bits that
could be independently
mapped to the external bus.
Groups should not be
overlapped.
each of the bit groups, for
example, B[0] = least significant
blue pixel bit
Freescale Semiconductor
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