MCIMX6S1AVM08ABR Freescale Semiconductor, MCIMX6S1AVM08ABR Datasheet - Page 99

• Manufacturer Part Number: MCIMX6S1AVM08ABR
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S1AVM08ABR

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 16 KB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: Parallel
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

1
2
3
4
4.11.10 Image Processing Unit (IPU) Module Parameters
The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor
and/or to a display device. This support covers all aspects of these activities:
Freescale Semiconductor
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal.
A Fast-mode I
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I
before the I2CLK line is released.
C
IC10
IC11
IC12
IC8
IC9
b
ID
•
•
•
= total capacitance of one bus line in pF.
Connectivity to relevant devices
Related image processing and manipulation: sensor image signal processing, display processing,
image conversions, and other related functions.
Synchronization and control capabilities, such as avoidance of tearing artifacts.
Data set-up time
Bus free time between a STOP and START condition
Rise time of both I2DAT and I2CLK signals
Fall time of both I2DAT and I2CLK signals
Capacitive load for each bus line (C
2
C-bus device can be used in a Standard-mode I
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
Table 68. I
Parameter
2
C Module Timing Parameters (continued)
b
—
)
cameras, displays, graphics accelerators, and TV encoders.
2
C-bus system, but the requirement of Set-up time (ID No IC7)
Min
250
4.7
—
—
—
Standard Mode
1000
Max
300
400
—
—
Electrical Characteristics
20 + 0.1C
20 + 0.1C
100
Fast Mode
Min
1.3
2
—
C-bus specification)
3
b
b
4
4
Max
300
300
400
—
—
Unit
pF
ns
µ
ns
ns
s
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