IS66WVE1M16BLL-55BLI-TR ISSI, IS66WVE1M16BLL-55BLI-TR Datasheet
IS66WVE1M16BLL-55BLI-TR
Specifications of IS66WVE1M16BLL-55BLI-TR
Related parts for IS66WVE1M16BLL-55BLI-TR
IS66WVE1M16BLL-55BLI-TR Summary of contents
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... Core Async/Page PSRAM Overview The IS66WVE1M16BLL is an integrated memory device containing 16Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 1M words by 16 bits. The device includes several power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and Deep Power Down mode ...
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... The system-configurable refresh mechanisms are accessed through the CR. A0~A19 CE# WE# Control OE# Logic LB# UB# ZZ# Rev Feb. 2012 Address Decode Logic 1024K X 16 Memory Array Configuration Register (CR) [ Functional Block Diagram] www.issi.com - SRAM@issi.com IS66WVE1M16BLL Input /Output DRAM Mux And Buffers DQ0~DQ15 2 ...
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... Rev Feb. 2012 OE UB CE# DQ10 A5 A6 DQ1 DQ11 A17 A7 DQ3 DQ12 NC A16 DQ4 DQ13 A14 A15 DQ5 A19 A12 A13 WE# A10 A11 A8 A9 [Top View] (Ball Down) www.issi.com - SRAM@issi.com IS66WVE1M16BLL 6 ZZ# DQ0 DQ2 VDD VSS DQ6 DQ7 NC 3 ...
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... TSOP-I (Top View) Notes : 1. The 48-pin TSOP-I package option is not yet available. Please contact SRAM marketing at sram@issi.com for additional information. Rev Feb. 2012 www.issi.com - SRAM@issi.com IS66WVE1M16BLL 4 ...
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... All VSSQ supply pins must be connected to Ground Data Inputs/Outputs (DQ0~DQ15) Address Input(A0~A19) Lower Byte select Upper Byte select Chip Enable/Select Output Enable Write Enable Sleep enable : When ZZ# is LOW, the CR can be loaded, or the device can enter one of two low-power modes ( DPD or PAR). www.issi.com - SRAM@issi.com IS66WVE1M16BLL 5 ...
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... DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled. Rev Feb. 2012 CE# WE# OE# UB#/LB www.issi.com - SRAM@issi.com IS66WVE1M16BLL DQ ZZ# Note 4 [15:0] H High-Z 2,5 H Data-Out 1,4 H Data-In 1,3 4,5 L High High High-Z 6 ...
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... Figure 1). During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 1: Power-Up Initialization Timing VDD=2.7V VDD VDDQ Rev Feb. 2012 tPU > 150us Device Initialization www.issi.com - SRAM@issi.com IS66WVE1M16BLL Device ready for normal operation 7 ...
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... WRITE operations, the level of OE “Don’t Care”; WE# overrides OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB#, whichever occurs first. WE# LOW time must be limited to tCEM. Figure 2. Asynchronous Read Operation Address DQ0- DQ15 CE# UB#/LB# OE# WE# Rev Feb. 2012 t = READ cycle Time RC VALID ADDRESS VALID DATA www.issi.com - SRAM@issi.com IS66WVE1M16BLL 8 ...
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... Figure 3. Asynchronous WRITE operation Address DQ0- DQ15 CE# UB#/LB# WE# OE# Rev Feb. 2012 t = WRITE cycle Time WC VALID ADDRESS VALID DATA < t CEM www.issi.com - SRAM@issi.com IS66WVE1M16BLL 9 ...
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... When both the UB#/LB# are disabled (HIGH) during an operation, the device prevents the data bus from receiving or transmitting data. Although the device may appear to be deselected, it remains in active mode as long as CE# remains LOW. Rev Feb. 2012 ADD0 ADD1 ADD2 APA APA D0 D1 www.issi.com - SRAM@issi.com IS66WVE1M16BLL ADD3 t APA ...
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... The setting selected must be for a temperature higher than the case temperature of the device. If the case temperature is +50°C, the system can minimize self refresh current consumption by selecting the +70°C setting. The +15°C and +45°C settings would result in inadequate refreshing and cause data corruption. Rev Feb. 2012 www.issi.com - SRAM@issi.com IS66WVE1M16BLL 11 ...
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... Driving ZZ# LOW puts the device in PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). The device should not be put into DPD using the CR software-access sequence. Rev Feb. 2012 www.issi.com - SRAM@issi.com IS66WVE1M16BLL 12 ...
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... Figure 5). The values placed on addresses A[19:0] are latched into the CR on the rising edge of CE# or WE#, whichever occurs first. LB#/UB# are “Don’t Care.” Access using ZZ# is WRITE only. Figure 5: Load Configuration Register Operation Using ZZ# Address CE# WE# t < 500ns ZZ# Rev Feb. 2012 VALID ADDRESS www.issi.com - SRAM@issi.com IS66WVE1M16BLL 13 ...
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... CR loading. Figure 6 : Configuration Register Write MAX Address ADDRESS DQ0- OUTPUT DQ15 DATA CE# Read UB#/LB# WE# OE# Notes : 0000h Rev Feb. 2012 MAX MAX ADDRESS ADDRESS OUTPUT *Note1 DATA Read Write www.issi.com - SRAM@issi.com IS66WVE1M16BLL MAX ADDRESS CR VALUE IN Write 14 ...
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... Figure 7 : Configuration Register Read Address MAX ADDRESS DQ0- OUTPUT DQ15 DATA CE# Read UB#/LB# WE# OE# Notes : 0000h Rev Feb. 2012 MAX MAX ADDRESS ADDRESS OUTPUT *Note1 DATA Read Write www.issi.com - SRAM@issi.com IS66WVE1M16BLL MAX ADDRESS CR VALUE OUT Read 15 ...
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... All Must be set to “0” Page mode disabled (default Page mode enabled +85°C (default +70° +45° +15° DPD enabled 1 = PAR enabled (default) Must be set to “0” 000 = Full array (default) 1 100 = None of array www.issi.com - SRAM@issi.com IS66WVE1M16BLL Remark 16 ...
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... Setting a lower temperature level would cause data to be corrupted due to insufficient refresh rate. Page Mode READ Operation (CR[7]) Default = Disabled The page mode operation bit determines whether page mode READ operations are enabled In the power-up default state, page mode is disabled. Rev Feb. 2012 C Operation o www.issi.com - SRAM@issi.com IS66WVE1M16BLL 17 ...
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... Rev Feb. 2012 Symbol VDD VDDQ VIH VIL VOH VOL ILI ILO Symbol -55 IDD1 - OUT -55 IDD1P -70 ISB www.issi.com - SRAM@issi.com IS66WVE1M16BLL Rating -0.5V to 4.0V or VDDQ + 0.3V -0. 4.0V -0. 4.0V -55°Cto + 150°C -40° 85°C + 260°C MIN MAX Unit 2.7 3.6 V 2.7 3.6 V VDDQ-0.4 VDDQ+0.2 V -0.20 0.4 V ...
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... Output timing ends at VDDQ/2. Figure 9. Output Load Circuit DUT Rev Feb. 2012 Conditions Symbol Izz Conditions T =+25°C; C f=1Mhz; VIN=0V ∫∫ Test Points ∫∫ Test Point 50Ω 30pF www.issi.com - SRAM@issi.com IS66WVE1M16BLL TYP MAX Unit Symbol MIN MAX Unit C 2.0 6 3.5 6 ...
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... High-Z (VDDQ/2) level toward either VOH or VOL. 3. Page mode enable only. Rev Feb. 2012 -55 -70 Min Max Min www.issi.com - SRAM@issi.com IS66WVE1M16BLL Unit Notes Max ...
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... WE# LOW must be limited to t Rev Feb. 2012 -55 -70 Min Max Min (8us) CEM www.issi.com - SRAM@issi.com IS66WVE1M16BLL Unit Notes Max ...
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... Initialization Period (required before normal operations) PU Rev Feb. 2012 -55 -70 Min Max Min 500 10 -55/-70 Min 5 150 10 Parameter www.issi.com - SRAM@issi.com IS66WVE1M16BLL Unit Note Max 500 ns Unit Notes Max -55/-70 Unit Min Max 150 us Notes 22 ...
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... OE# t CDZZ ZZ# Figure 12: DPD Entry and Exit Timing t CDZZ ZZ# CE# Rev Feb. 2012 tPU > 150us Device Initialization t WC OPCODE ZZWE t (MIN) ZZ www.issi.com - SRAM@issi.com IS66WVE1M16BLL VDD(MIN) Device ready for normal operation Device ready for normal operation 23 ...
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... OLZ VALID ADDRESS t PC VALID VALID ADDRESS ADDRESS ADDRESS APA VALID VALID OUTPUT OUTPUT OLZ t OE www.issi.com - SRAM@issi.com IS66WVE1M16BLL VALID OUTPUT BHZ t OHZ VALID VALID ADDRESS VALID VALID OUTPUT OUTPUT BHZ t OHZ 24 ...
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... Figure 15: CE#-Controlled Asynchronous WRITE Address DQ0- DQ15 CE# UB#/LB# OE# WE# Rev Feb. 2012 t WC VALID ADDRESS WHZ www.issi.com - SRAM@issi.com IS66WVE1M16BLL t WR VALID INPUT CPH 25 ...
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... Figure 16: LB#/UB#-Controlled Asynchronous WRITE Address DQ0- DQ15 UB#/LB# OE# WE# Rev Feb. 2012 t WC VALID ADDRESS WHZ www.issi.com - SRAM@issi.com IS66WVE1M16BLL t WR VALID INPUT ...
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... Figure 17: WE#-Controlled Asynchronous WRITE Address DQ0- DQ15 CE# UB#/LB OE# t WPH WE# Rev Feb. 2012 t WC VALID ADDRESS WHZ www.issi.com - SRAM@issi.com IS66WVE1M16BLL t WR VALID INPUT ...
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... Config. Speed Order Part No. (ns) 1Mx16 55 IS66WVE1M16BLL-55BLI 70 IS66WVE1M16BLL-70BLI Notes : 1. The 48-pin TSOP-I package option is not yet available. Please contact SRAM marketing at sram@issi.com for additional information. Rev Feb. 2012 Package 48-ball TFBGA, Lead-free 48-ball TFBGA, Lead-free www.issi.com - SRAM@issi.com IS66WVE1M16BLL 28 ...
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... TSOP-I package configuration Rev Feb. 2012 www.issi.com - SRAM@issi.com IS66WVE1M16BLL 29 ...
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... Rev Feb. 2012 www.issi.com - SRAM@issi.com IS66WVE1M16BLL 30 ...