Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 143

• Manufacturer Part Number: Z8F011ASH020EG2156
• Description: 8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F011ASH020EG2156

• Rohs: yes
• Core: eZ8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 1 KB
• Data Ram Size: 256 B
• On-chip Adc: No
• Package / Case: SOIC-20
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

®
Z8 Encore!
F0830 Series
Product Specification
125
Option Bit Types
This section describes the two types of Flash option bits offered in the F0830 Series.
User Option Bits
The user option bits are contained in the first two bytes of program memory. User access
to these bits is provided because these locations contain application specific device config-
urations. The information contained here is lost when page 0 of program memory is
erased.
Trim Option Bits
The trim option bits are contained in the information page of the Flash memory. These bits
are factory programmed values required to optimize the operation of onboard analog cir-
cuitry and cannot be permanently altered by the user. Program memory can be erased
without endangering these values. It is possible to alter working values of these bits by
accessing the trim bit address and data registers, but these working values are lost after a
power loss.
There are 32 bytes of trim data. To modify one of these values, the user code must first
write a value between
and
into the Trim Bit Address Register. The next write to
00H
1FH
the Trim Bit Data Register changes the working value of the target trim data byte.
Reading the trim data requires the user code to write a value between
and
into the
00H
1FH
Trim Bit Address Register. The next read from the Trim Bit Data Register returns the
working value of the target trim data byte.
Note:
The trim address range is from information address
only. The remaining informa-
20–3F
tion page is not accessible via the Trim Bit Address and Data registers.
During reset, the first 43 system clock cycles perform 43 Flash accesses. The six bits of
the counter provide the lower six bits of the Flash memory address. All other address bits
are set to 0. The option bit registers use the 6-bit address from the counter as an address
and latch the data from the Flash on the positive edge of the IPO clock, allowing for a
maximum of 344-bits (43 bytes) of option information to be read from Flash.
Because option information is stored in both the first two bytes of program memory and in
the information area of Flash memory, the data must be placed in specific locations to be
read correctly. In this case, the first two bytes at addresses 0 and 1 in program memory are
read out and the remainder of the bytes are read out of the Flash information area.
PS025113-1212
Operation