Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 74

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Z8F011ASH020EG2156

Manufacturer Part Number
Z8F011ASH020EG2156
Description
8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F011ASH020EG2156

Rohs
yes
Core
eZ8
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
1 KB
Data Ram Size
256 B
On-chip Adc
No
Package / Case
SOIC-20
Mounting Style
SMD/SMT
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
PS025113-1212
Caution:
Interrupt Vectors and Priority
Interrupt Assertion
Interrupts are globally disabled by any of the following actions:
The Interrupt Controller supports three levels of interrupt priority. Level 3 is the highest
priority, level 2 is the second highest priority and level 1 is the lowest priority. If all of the
interrupts are enabled with identical interrupt priority (all as level 2 interrupts, for exam-
ple), the interrupt priority is assigned from highest to lowest as specified in
page 54. Level 3 interrupts are always assigned higher priority than level 2 interrupts and
level 2 interrupts are assigned higher priority than level 1 interrupts. Within each interrupt
priority level (level 1, level 2 or level 3), priority is assigned as specified in Table 34,
above. Reset, Watchdog Timer interrupt (if enabled), primary oscillator fail trap, Watch-
dog Oscillator fail trap and illegal instruction trap always have highest (level 3) priority.
Interrupt sources assert their interrupt requests for only a single system clock period (sin-
gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond-
ing bit in the interrupt request register is cleared. Writing 0 to the corresponding bit in the
interrupt request register clears the interrupt request.
Example 1.
Zilog recommends not using a coding style that clears bits in the Interrupt Request reg-
isters. All incoming interrupts received between execution of the first LDX command
and the final LDX command are lost. See Example 1, which follows.
Writing 1 to the IRQE bit in the Interrupt Control Register
Execution of a
eZ8 CPU acknowledgement of an interrupt service request from the Interrupt Control-
ler
Writing a 0 to the IRQE bit in the Interrupt Control Register
Reset
Execution of a trap instruction
Illegal instruction Trap
Primary oscillator fail trap
Watchdog Oscillator fail trap
A poor coding style that can result in lost interrupt requests:
DI
(disable interrupt) instruction
Z8 Encore!
Product Specification
®
F0830 Series
Table 34
Operation
on
56

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