NAND04GW3B2DN6E NUMONYX, NAND04GW3B2DN6E Datasheet - Page 16

• Manufacturer Part Number: NAND04GW3B2DN6E
• Description: IC FLASH 4GBIT 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND04GW3B2DN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 4G (512M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signals description
3
3.1
3.2
3.3
3.4
3.5
3.6
16/72
Signals description
See
connected to this device.
Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 input the selected address, output the data during a read operation, or
input a command or data during a write operation. The inputs are latched on the rising edge
of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are
disabled.
Inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 devices. They output the data during a read
operation or input data during a write operation. Command and address inputs only require
I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
Address latch enable (AL)
The address latch enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
Command latch enable (CL)
The command latch enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
Chip enable (E)
The Chip Enable input, E, activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, V
High, V
standby mode.
Read enable (R)
The Read Enable pin, R, controls the sequential data output during read operations. Data is
valid t
column address counter by one.
Figure 2: Logic diagram
RLQV
IH
, while the device is busy, the device remains selected and does not go into
after the falling edge of R. The falling edge of R also increments the internal
and
Table 3: Signals names
IL
, the device is selected. If Chip Enable goes
for a brief overview of the signals
NAND04G-B2D, NAND08G-BxC