MT48H4M16LFB4-75:H TR Micron Technology Inc, MT48H4M16LFB4-75:H TR Datasheet - Page 14

• Manufacturer Part Number: MT48H4M16LFB4-75:H TR
• Description: IC SDRAM 64MBIT 133MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-75:H TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1392-2

Commands
Table 5:
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE or deep power-down
(Enter deep power-down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER/LOAD EXTENDED MODE
REGISTER
Write enable/output enable
Write inhibit/output High-Z
Truth Table 1 – Commands and DQM Operation
Note 1; notes appear below table
Notes:
10. The purpose of the BURST TERMINATE command is to stop a data burst; thus, the command
Table 5 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional truth tables appear following “Opera-
tions” on page 18; these tables provide current state/next state information.
1. CKE is HIGH for all commands shown except SELF REFRESH and deep power-down.
2. A0–A11 define op-code written to mode register.
3. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0–A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersis-
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
8. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock
9. This command is BURST TERMINATE when CKE is HIGH and deep power-down when CKE is
tent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank
is being read from or written to.
and BA0, BA1 are “Don’t Care.”
for CKE.
delay). LDQM controls DQ0–7, UDQM controls DQ8–15.
LOW.
could coincide with data on the bus. However, the DQ column reads a “Don’t Care” state to
illustrate that the BURST TERMINATE command can occur when there is no data present.
CS# RAS# CAS# WE#
H
X
X
L
L
L
L
L
L
L
L
14
X
H
H
H
H
X
X
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
X
X
L
L
L
L
64Mb: 4 Meg x 16 Mobile SDRAM
H
H
H
H
X
X
X
L
L
L
L
DQM
L/H
L/H
X
X
X
X
X
X
X
H
L
Bank/Row
Bank, A10
Bank/Col
Bank/Col
©2006 Micron Technology, Inc. All rights reserved.
Op-code
ADDR
X
X
X
X
X
X
High-Z
Active
Commands
Valid
DQ
X
X
X
X
X
X
X
X
Notes
9, 10
6, 7
3
4
4
5
2
8
8