MT48H4M16LFB4-75:H TR Micron Technology Inc, MT48H4M16LFB4-75:H TR Datasheet - Page 17

• Manufacturer Part Number: MT48H4M16LFB4-75:H TR
• Description: IC SDRAM 64MBIT 133MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-75:H TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1392-2

Deep Power-Down
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
except CKE is disabled (LOW). When the SELF REFRESH command is registered, all the
inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must
remain LOW.
During self refresh, the device is refreshed as identified in the extended mode register
PASR settings. After self refresh mode is engaged, the SDRAM provides its own internal
clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain
in self refresh mode for a minimum period equal to
mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock pin) prior to CKE going back HIGH. When CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands should be issued at
once and then every 15.625µs or less, because SELF REFRESH and AUTO REFRESH use
the row refresh counter.
Deep power-down is an operating mode used to achieve maximum power reduction by
eliminating the power to the memory array. Data is not retained after the device enters
deep power-down mode.
This mode is entered by having all banks idle then CS# and WE# held LOW with RAS#
and CAS# held HIGH at the rising edge of the clock, while CKE is LOW. This mode is
exited by asserting CKE HIGH.
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
64Mb: 4 Meg x 16 Mobile SDRAM
t
RAS and may remain in self refresh
t
XSR because time is
©2006 Micron Technology, Inc. All rights reserved.
Commands