MT48H4M16LFB4-75:H TR Micron Technology Inc, MT48H4M16LFB4-75:H TR Datasheet - Page 38

• Manufacturer Part Number: MT48H4M16LFB4-75:H TR
• Description: IC SDRAM 64MBIT 133MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-75:H TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1392-2

PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
9. Burst in bank n continues as initiated.
represented by the current state only.
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
burst has been interrupted by bank m’s burst.
charge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 10 on
page 20).
charge), the WRITE to bank m will interrupt the READ on bank n when registered (see
Figure 12 on page 22 and Figure 13 on page 22). DQM should be used one clock prior to the
WRITE command to prevent bus contention.
charge), the READ to bank m will interrupt the WRITE on bank n when registered (see
Figure 20 on page 26), with the data-out appearing CL later. The last valid WRITE to bank n
will be data-in registered one clock prior to the READ to bank m.
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered (see
Figure 18 on page 25). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
the READ to bank m will interrupt the READ on bank n, CL later (see Figure 27 on page 31).
The PRECHARGE to bank n will begin when the READ to bank m is registered.
the WRITE to bank m will interrupt the READ on bank n when registered (see Figure 28 on
page 32). DQM should be used two clocks prior to the WRITE command to prevent bus con-
tention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered.
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later (see Figure 29 on page 33). The PRECHARGE to bank n will begin after
t
bank n will be data-in registered one clock prior to the READ to bank m.
the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE
to bank n will begin after
istered (see Figure 30 on page 33). The last valid WRITE to bank n will be data registered
one clock to the WRITE to bank m.
WR is met, where
t
WR begins when the READ to bank m is registered. The last valid WRITE
t
WR is met, where
38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64Mb: 4 Meg x 16 Mobile SDRAM
t
WR begins when the WRITE to bank m is reg-
©2006 Micron Technology, Inc. All rights reserved.
Operations