MT48H4M16LFB4-75:H TR Micron Technology Inc, MT48H4M16LFB4-75:H TR Datasheet - Page 19

• Manufacturer Part Number: MT48H4M16LFB4-75:H TR
• Description: IC SDRAM 64MBIT 133MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-75:H TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1392-2

Figure 8:
READs
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
Meeting
Note:
t
RCD (MIN) when 2 <
Command
READ bursts are initiated with a READ command, as shown in Figure 8.
The starting column and bank addresses are provided with the READ command, and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 5 on page 11 shows general
timing for each possible CL setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z.
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x = CL - 1.
This is shown in Figure 10 on page 20 for CL = 2 and CL = 3; data element n + 3 is either
the last of a burst of four or the last desired of a longer burst. The Mobile SDRAM uses a
pipelined architecture and therefore does not require the 2n rule associated with a
prefetch architecture. A READ command can be initiated on any clock cycle following a
previous READ command. Full-speed random read accesses can be performed to the
same bank, as shown in Figure 11 on page 21, or each subsequent READ may be
performed to a different bank.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
For the generic READ commands used in the following illustrations, auto precharge is
disabled.
CLK
ACTIVE
T0
t
RCD (MIN)/
NOP
T1
19
t
RCD
t
CK < 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
NOP
64Mb: 4 Meg x 16 Mobile SDRAM
READ or
WRITE
T3
Don’t Care
©2006 Micron Technology, Inc. All rights reserved.
T4
Operations