N25Q128A13BF840F NUMONYX, N25Q128A13BF840F Datasheet - Page 33

• Manufacturer Part Number: N25Q128A13BF840F
• Description: IC SRL FLASH 128MB NMX 8-VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BF840F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

N25Q128 - 3 V
6.1
6.1.1
6.1.2
6.1.3
6.1.4
Legacy SPI Status Register
The Status Register contains a number of status and control bits that can be read or set by
specific instructions: Read Status Register (RDSR) and Write Status Register (WRSR). This
is available in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI).
Table 2.
WIP bit
The Write In Progress (WIP) bit set to 1 indicates that the memory is busy with a Write
Status Register, (WRSR), Write Non-Volatile Configuration Register (WRNVCR), Write
Volatile Configuration Register (WRVCR), Write Volatile Enhanced Configuration Register
(WRVECR), Program or Erase cycle instruction is accepted.
WEL bit
The Write Enable Latch (WEL) bit set to 1 indicates that the internal Write Enable Latch is
set. When set to 0 the internal Write Enable Latch is reset and no Write to Lock Register
(WRLR), Write Non-Volatile Configuration Register (WRNVCR), Write Volatile Configuration
Register (WRVCR), Write Volatile Enhanced Configuration Register (WRVECR) instruction,
Program or Erase instruction is accepted
BP3, BP2, BP1, BP0 bits
The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the
area to be software protected against Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) instruction. When one or more of the Block
Protect (BP3, BP2, BP1, BP0) bits is set to 1, the relevant memory area, as defined in
10.: Protected area sizes, Upper (TB bit = 0)
bit =
(BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has
not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect
(BP3, BP2, BP1, BP0) bits are 0.
TB bit
The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Register
(WRSR) instruction provided that the Write Enable (WREN) instruction has been issued.
Status register write protect
SRWD
1), becomes protected against all program and erase instructions. The Block Protect
b7
Status register format
BP3
Top/bottom bit
TB
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BP2
and
Block protect bits
Table 11.: Protected area sizes, Lower (TB
BP1
Volatile and Non Volatile Registers
Write enable latch bit
BP0
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WEL
Write in progress bit
WIP
b0
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Table