N25Q128A13BF840F NUMONYX, N25Q128A13BF840F Datasheet - Page 93

• Manufacturer Part Number: N25Q128A13BF840F
• Description: IC SRL FLASH 128MB NMX 8-VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BF840F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

N25Q128 - 3 V
Note:
9.2.4
Note:
DQ0
DQ1
C
S
DQ0
DQ1
C
S
0
0
Instruction
Instruction
1
1
2
2
the device is set in DIO-SPI mode, by sending to the memory indifferently one of the 3
instructions codes: 0Bh, 3Bh or BBh, the effect is exactly the same. The 3 instruction codes
are all accepted to help the application code porting from Extended SPI protocol to DIO-SPI
protocol.
Except for the parallelizing on two pins of the instruction code, the Dual Command Fast
Read instruction functionality is exactly the same as the Dual I/O Fast Read of the Extended
SPI protocol.
The dummy bits can not be parallelized since these clock cycles are requested to perform
the internal reading operation.
Figure 46. Dual Command Fast Read instruction and data-out sequence DIO-SPI
Read OTP (ROTP)
The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the DIO-SPI
protocol. The instruction functionality is exactly the same as the Read OTP instruction of the
Extended SPI protocol; the only difference is that in the DIO-SPI protocol instruction code,
address and output data are all parallelized on the two pins DQ0 and DQ1.
The dummy bits can not be parallelized since these clock cycles are requested to perform
the internal reading operation.
Figure 47. Read OTP instruction and data-out sequence DIO-SPI
3
3
23 21 19 17
22 20 18 16
23 21 19 17
22 20 18 16
4
4
5
5
6
6
7
7
24-Bit Address
24-Bit Address
15 13 11 9
14 12 10 8
15 13 11 9
14 12 10 8
8
8
9 10 11
9 10 11
12 13 14 15
12 13 14 15
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Dummy cycles
Dummy cycles
7
MSB
6
7
MSB
6
Data Out 1
Data Out 1
©2010 Micron Technology, Inc. All rights reserved.
5
4
5
4
Dual_Command_Fast_Read
3
2
3
2
1
0
1
0
Dual_Read_OTP
MSB
6
7
MSB
6
7
Data Out n
Instructions
Data Out n
4
5
4
5
2
3
2
3
0
1
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0
1