N25Q128A13BF840F NUMONYX, N25Q128A13BF840F Datasheet - Page 65

• Manufacturer Part Number: N25Q128A13BF840F
• Description: IC SRL FLASH 128MB NMX 8-VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BF840F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

N25Q128 - 3 V
9.1.9
DQ0
DQ1
DQ0
DQ1
Read OTP (ROTP)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a configurable
number of dummy clock cycles. Each bit is latched in on the rising edge of Serial Clock (C).
Then the memory contents at that address are shifted out on Serial Data output (DQ1).
Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock
(C). The address is automatically incremented to the next higher address after each byte of
data is shifted out.
There is no rollover mechanism with the Read OTP (ROTP) instruction. This means that the
Read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read. All other
bytes outside the OTP area are “Don’t Care.”
The Read OTP (ROTP) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read OTP (ROTP)
instruction issued while an Erase or Program cycle is in progress, is rejected without having
any effect on the cycle that is in progress.
Figure 18. Read OTP instruction and data-out sequence
C
S
S
C
7
32 33 34
0
6
1
High Impedance
Dummy cycles
5
2
Instruction
4
35
3
3
36 37 38 39 40 41 42 43 44 45 46
4
2
5
1
6
0
7
MSB
7
23
8
6
22 21
9 10
5
DATA OUT 1
24-bit address
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4
3
3
28 29 30 31
2
2
1
1
0
47
0
MSB
7
6
5
DATA OUT n
©2010 Micron Technology, Inc. All rights reserved.
4
3
2
1
0
MSB
Instructions
7
65/157