CY7C1512AV18-250BZI Cypress Semiconductor Corp, CY7C1512AV18-250BZI Datasheet
CY7C1512AV18-250BZI
Manufacturer Part Number
CY7C1512AV18-250BZI
Description
IC SRAM 72MBIT 250MHZ 165TFBGA
Manufacturer
Cypress Semiconductor Corp
Datasheets
1.CY7C1514AV18-167BZXC.pdf
(28 pages)
2.CY7C1512AV18-200BZXC.pdf
(26 pages)
3.CY7C1512AV18-200BZXC.pdf
(24 pages)
4.CY7C1514AV18-200BZXI.pdf
(28 pages)
Specifications of CY7C1512AV18-250BZI
Format - Memory
RAM
Memory Type
SRAM - Synchronous, QDR II
Memory Size
72M (4M x 18)
Speed
250MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
-40°C ~ 85°C
Package / Case
165-TFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1512AV18-250BZI
Manufacturer:
CYPRESS
Quantity:
490
Company:
Part Number:
CY7C1512AV18-250BZI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C1512AV18-250BZIT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Cypress Semiconductor Corporation
Document #: 001-06984 Rev. *B
Features
Configurations
CY7C1510AV18 – 8M x 8
CY7C1525AV18 – 8M x 9
CY7C1512AV18 – 4M x 18
CY7C1514AV18 – 2M x 36
• Separate Independent Read and Write Data Ports
• 250-MHz clock for high bandwidth
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
• Two input clocks (K and K) for precise DDR timing
• Two input clocks for output data (C and C) to minimize
• Echo clocks (CQ and CQ) simplify data capture in high
• Single multiplexed address input bus latches address
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• QDR-II operates with 1.5 cycle read latency when DLL
• Operates like a QDR I device with 1 cycle read latency
• Available in x8, x9, x18, and x36 configurations
• Full data coherency, providing most current data
• Core V
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in lead-free and non-lead free packages
• Variable drive HSTL output buffers
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
— Supports concurrent transactions
Write ports (data transferred at 500 MHz) @ 250 MHz
— SRAM uses rising edges only
clock-skew and flight-time mismatches
speed systems
inputs for both Read and Write ports
is enabled
in DLL off mode
DD
= 1.8V (±0.1V); I/O V
DDQ
= 1.4V to V
•
198 Champion Court
72-Mbit QDR-II™ SRAM 2-Word Burst
DD
PRELIMINARY
Functional Description
The CY7C1510AV18, CY7C1525AV18, CY7C1512AV18 and
CY7C1514AV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write Port has dedicated Data Inputs to
support Write operations. QDR-II architecture has separate
data inputs and data outputs to completely eliminate the need
to “turn-around” the data bus required with common I/O
devices. Access to each port is accomplished through a
common address bus. The Read address is latched on the
rising edge of the K clock and the Write address is latched on
the rising edge of the K clock. Accesses to the QDR-II Read
and Write ports are completely independent of one another. In
order to maximize data throughput, both Read and Write ports
are equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with two 8-bit words
(CY7C1510AV18) or 9-bit words (CY7C1525AV18) or 18-bit
words (CY7C1512AV18) or 36-bit words (CY7C1514AV18)
that burst sequentially into or out of the device. Since data can
be transferred into and out of the device on every rising edge
of both input clocks (K and K and C and C), memory bandwidth
is maximized while simplifying system design by eliminating
bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
•
San Jose
,
CA 95134-1709
Revised September 20, 2006
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
Architecture
•
408-943-2600
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