CY7C1512AV18-250BZI Cypress Semiconductor Corp, CY7C1512AV18-250BZI Datasheet - Page 10

• Manufacturer Part Number: CY7C1512AV18-250BZI
• Description: IC SRAM 72MBIT 250MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512AV18-250BZI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 001-06984 Rev. *B
Write Cycle Descriptions
Write Cycle Descriptions
Note:
9. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS
BWS
BWS
portions of a write cycle, as long as the set-up and hold requirements are achieved.
H
H
L
L
0
H
H
H
H
0
L
L
L
L
/NWS
L-H
L-H
0
K
–
–
BWS
L-H
L-H
1
K
–
–
H
H
H
H
L
L
L
L
/NWS
During the Data portion of a Write sequence:
CY7C1525AV18 − the single byte (D
During the Data portion of a Write sequence:
CY7C1525AV18 − the single byte (D
No data is written into the devices during this portion of a write operation.
No data is written into the devices during this portion of a write operation.
1
(CY7C1510AV18 and CY7C1512AV18)
(CY7C1525AV18)
L-H
L-H
L-H
L-H
K
–
–
–
–
L-H During the Data portion of a Write sequence:
L-H During the Data portion of a Write sequence:
L-H During the Data portion of a Write sequence:
L-H No data is written into the devices during this portion of a write operation.
K
–
–
–
–
During the Data portion of a Write sequence:
CY7C1510AV18 − both nibbles (D
CY7C1512AV18 − both bytes (D
CY7C1510AV18 − both nibbles (D
CY7C1512AV18 − both bytes (D
During the Data portion of a Write sequence:
CY7C1510AV18 − only the lower nibble (D
remain unaltered,
CY7C1512AV18 − only the lower byte (D
remain unaltered.
CY7C1510AV18 − only the lower nibble (D
remain unaltered,
CY7C1512AV18 − only the lower byte (D
remain unaltered.
During the Data portion of a Write sequence:
CY7C1510AV18 − only the upper nibble (D
remain unaltered,
CY7C1512AV18 − only the upper byte (D
remain unaltered.
CY7C1510AV18 − only the upper nibble (D
remain unaltered,
CY7C1512AV18 − only the upper byte (D
remain unaltered.
No data is written into the devices during this portion of a write operation.
PRELIMINARY
[8:0]
[8:0]
) is written into the device
) is written into the device
Comments
[3, 9]
0,
NWS
1,
[17:0]
[17:0]
BWS
Comments
[7:0]
[7:0]
) are written into the device.
) are written into the device.
0
) are written into the device,
) are written into the device,
,BWS
[8:0]
[8:0]
[17:9]
[17:9]
[3:0]
[3:0]
[7:4]
[7:4]
1
) is written into the device. D
) is written into the device. D
,BWS
) is written into the device. D
) is written into the device. D
) is written into the device. D
) is written into the device. D
) is written into the device. D
) is written into the device. D
2
and BWS
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
3
can be altered on different
Page 10 of 26
[17:9]
[17:9]
[8:0]
[8:0]
[7:4]
[7:4]
[3:0]
[3:0]
will
will
will
will
will
will
will
will
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