CY7C1512AV18-250BZI Cypress Semiconductor Corp, CY7C1512AV18-250BZI Datasheet - Page 7

• Manufacturer Part Number: CY7C1512AV18-250BZI
• Description: IC SRAM 72MBIT 250MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512AV18-250BZI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 001-06984 Rev. *B
Pin Definitions
Functional Overview
The CY7C1510AV18,CY7C1525AV18,CY7C1512AV18 and
CY7C1514AV18 are synchronous pipelined Burst SRAMs
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read Port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-II completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of two 8-bit data transfers in the case of
CY7C1510AV18, two 9-bit data transfers in the case of
CY7C1525AV18, two 18-bit data transfers in the case of
K
K
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
V
V
V
V
V
V
SS
SS
REF
DD
SS
DDQ
Pin Name
/144M
/ 288M
(continued)
Power Supply
Power Supply
Input-Clock
Input-Clock
Echo Clock
Echo Clock
Reference
Ground
Output
Input-
Input
Input
Input
Input
Input
Input
Input
N/A
I/O
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q
are initiated on the rising edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is
generated with respect to K. The timings for the echo clocks are shown in the AC Timing
table.
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is
generated with respect to K. The timings for the echo clocks are shown in the AC Timing
table.
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. CQ, CQ, and Q
where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be
connected directly to V
cannot be connected directly to GND or left unconnected.
DLL Turn Off - Active LOW. Connecting this pin to ground will turn off the DLL inside
the device. The timings in the DLL turned off operation will be different from those listed
in this data sheet. For normal operation, this pin can be connected to a pull-up through
a 10-Kohm or less pull-up resistor. The device will behave in QDR-I mode when the DLL
is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR-I timing.
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Not connected to the die. Can be tied to any voltage level.
Address expansion for 144M. Can be tied to any voltage level.
Address expansion for 288M. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
Power supply inputs to the core of the device.
Ground for the device.
Power supply inputs for the outputs of the device.
PRELIMINARY
DDQ
CY7C1512AV18 and two 36-bit data transfers in the case of
CY7C1514AV18, in one clock cycle.
This device operates with a read latency of one and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to V
with a read latency of one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are
referenced from the rising edge of the input clocks (K and K)
and all output timings are referenced to the rising edge of
output clocks (C and C or K and K when in single clock mode).
All synchronous data inputs (D
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q
, which enables the minimum impedance mode. This pin
Pin Description
SS
[x:0]
then the device will behave in QDR-I mode
[x:0]
[x:0]
when in single clock mode. All accesses
output impedance are set to 0.2 x RQ,
when in single clock mode.
[x:0]
[x:0]
) outputs pass through output
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
) inputs pass through input
Page 7 of 26
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