CY7C1512AV18-250BZI Cypress Semiconductor Corp, CY7C1512AV18-250BZI Datasheet - Page 6

• Manufacturer Part Number: CY7C1512AV18-250BZI
• Description: IC SRAM 72MBIT 250MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512AV18-250BZI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 001-06984 Rev. *B
Pin Definitions
D
WPS
NWS
BWS
BWS
A
Q
RPS
C
C
[x:0]
[x:0]
Pin Name
0
0
2
, BWS
, BWS
,NWS
1
1
3
,
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-Clock
Input-Clock
Outputs-
Input-
Input-
Input-
Input-
Input-
I/O
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1510AV18 - D
CY7C1525AV18 - D
CY7C1512AV18 - D
CY7C1514AV18 - D
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D
Nibble Write Select 0,1 − active LOW. (CY7C1510AV18 Only) Sampled on the rising
edge of the K and K clocks during write operations. Used to select which nibble is written
into the device during the current portion of the write operations.Nibbles not written
remain unaltered.NWS
are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause
the corresponding nibble of data to be ignored and not written into the device.
Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and
K clocks during write operations. Used to select which byte is written into the device
during the current portion of the write operations. Bytes not written remain unaltered.
CY7C1525AV18 − BWS
CY7C1512AV18 − BWS
CY7C1514AV18 − BWS
and BWS
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte
Write Select will cause the corresponding byte of data to be ignored and not written into
the device.
Address Inputs. Sampled on the rising edge of the K (read address) and K (write
address) clocks during active read and write operations. These address inputs are multi-
plexed for both Read and Write operations. Internally, the device is organized as 8M x 8
(2 arrays each of 4M x 8) for CY7C1510AV18, 8M x 9 (2 arrays each of 4M x 9) for
CY7C1525AV18, 4M x 18 (2 arrays each of 2M x 18) for CY7C1512AV18 and 2M x 36
(2 arrays each of 1M x 36) for CY7C1514AV18. Therefore, only 22 address inputs are
needed to access the entire memory array of CY7C1510AV18 and CY7C1525AV18, 21
address inputs for CY7C1512AV18 and 20 address inputs for CY7C1514AV18. These
inputs are ignored when the appropriate port is deselected.
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q
CY7C1510AV18 − Q
CY7C1525AV18 − Q
CY7C1512AV18 − Q
CY7C1514AV18 − Q
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically tri-stated following the next rising edge of the C clock. Each
read access consists of a burst of two sequential transfers.
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the
Read data from the device. C and C can be used together to deskew the flight times of
various devices on the board back to the controller. See application example for further
details.
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the
Read data from the device. C and C can be used together to deskew the flight times of
various devices on the board back to the controller. See application example for further
details.
[x:0]
are automatically tri-stated.
3
controls D
PRELIMINARY
[7:0]
[8:0]
[17:0]
[35:0]
[7:0]
[8:0]
[17:0]
[35:0]
[35:27].
0
0
0
0
controls D
controls D
controls D
controls D
[3:0]
Pin Description
[8:0]
[8:0]
[8:0]
and NWS
[x:0]
, BWS
, BWS
to be ignored.
1
1
controls D
controls D
1
controls D
[17:9]
[17:9]
[7:4]
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
.
,BWS
.All Nibble Write Selects
2
controls D
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